From f8fc5d8c04c1c85e4bf968ed774128bae177d813 Mon Sep 17 00:00:00 2001
From: Neel Gala <neelgala@gmail.com>
Date: Thu, 4 Feb 2021 12:38:04 +0530
Subject: [PATCH] fix logging for fcsr (#639)

Co-authored-by: Neel Gala <neelgala@incoresemi.com>
---
 riscv/processor.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 81ffde87..2629b6cc 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -1294,6 +1294,7 @@ void processor_t::set_csr(int which, reg_t val)
       LOG_CSR(CSR_MSTATUS);
       LOG_CSR(CSR_FFLAGS);
       LOG_CSR(CSR_FRM);
+      LOG_CSR(CSR_FCSR);
       break;
     case CSR_VCSR:
       LOG_CSR(CSR_MSTATUS);