Add gva field to trap_breakpoint

So I can fix breakpoints next to properly report gva.

riscv/execute.cc

@@ -329,7 +329,7 @@ void processor_t::step(size_t n)
           enter_debug_mode(DCSR_CAUSE_HWBP);
           break;
         case ACTION_DEBUG_EXCEPTION: {
-          trap_breakpoint trap(t.address);
+          trap_breakpoint trap(/*gva*/false, t.address);
           take_trap(trap, pc);
           break;
         }

riscv/insns/c_ebreak.h

@@ -1,2 +1,2 @@
 require_extension('C');
-throw trap_breakpoint(pc);
+throw trap_breakpoint(/*gva*/false, pc);

riscv/insns/ebreak.h

@@ -1 +1 @@
-throw trap_breakpoint(pc);
+throw trap_breakpoint(/*gva*/false, pc);

riscv/trap.h

@@ -68,6 +68,12 @@ class mem_trap_t : public trap_t
   const char* name() { return "trap_"#x; } \
 };
 
+#define DECLARE_INST_WITH_GVA_TRAP(n, x) class trap_##x : public insn_trap_t {  \
+ public: \
+  trap_##x(bool gva, reg_t tval) : insn_trap_t(n, gva, tval) {} \
+  const char* name() { return "trap_"#x; } \
+};
+
 #define DECLARE_MEM_TRAP(n, x) class trap_##x : public mem_trap_t { \
  public: \
   trap_##x(bool gva, reg_t tval, reg_t tval2, reg_t tinst) : mem_trap_t(n, gva, tval, tval2, tinst) {} \
@@ -83,7 +89,7 @@ class mem_trap_t : public trap_t
 DECLARE_MEM_TRAP(CAUSE_MISALIGNED_FETCH, instruction_address_misaligned)
 DECLARE_MEM_TRAP(CAUSE_FETCH_ACCESS, instruction_access_fault)
 DECLARE_INST_TRAP(CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction)
-DECLARE_INST_TRAP(CAUSE_BREAKPOINT, breakpoint)
+DECLARE_INST_WITH_GVA_TRAP(CAUSE_BREAKPOINT, breakpoint)
 DECLARE_MEM_TRAP(CAUSE_MISALIGNED_LOAD, load_address_misaligned)
 DECLARE_MEM_TRAP(CAUSE_MISALIGNED_STORE, store_address_misaligned)
 DECLARE_MEM_TRAP(CAUSE_LOAD_ACCESS, load_access_fault)