rvv: add new singed/unsiged extension instructions

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

riscv/decode.h

@@ -1683,6 +1683,46 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
   } \
   p->VU.vstart = 0;
 
+//
+// vector: sign/unsiged extension
+#define VI_VV_EXT(div, type) \
+  require(insn.rd() != insn.rs2()); \
+  require_vm; \
+  reg_t from = P.VU.vsew / div; \
+  require(from >= e8 && from <= e64); \
+  require_align(insn.rd(), P.VU.vflmul); \
+  require_align(insn.rs2(), P.VU.vflmul / div); \
+  require_noover(insn.rd(), P.VU.vflmul, insn.rs2(), P.VU.vflmul / div); \
+  reg_t pat = (((P.VU.vsew >> 3) << 4) | from >> 3); \
+  VI_GENERAL_LOOP_BASE \
+  VI_LOOP_ELEMENT_SKIP(); \
+    switch (pat) { \
+      case 0x21: \
+        P.VU.elt<type##16_t>(rd_num, i, true) = P.VU.elt<type##8_t>(rs2_num, i); \
+        break; \
+      case 0x41: \
+        P.VU.elt<type##32_t>(rd_num, i, true) = P.VU.elt<type##8_t>(rs2_num, i); \
+        break; \
+      case 0x81: \
+        P.VU.elt<type##64_t>(rd_num, i, true) = P.VU.elt<type##8_t>(rs2_num, i); \
+        break; \
+      case 0x42: \
+        P.VU.elt<type##32_t>(rd_num, i, true) = P.VU.elt<type##16_t>(rs2_num, i); \
+        break; \
+      case 0x82: \
+        P.VU.elt<type##64_t>(rd_num, i, true) = P.VU.elt<type##16_t>(rs2_num, i); \
+        break; \
+      case 0x84: \
+        P.VU.elt<type##64_t>(rd_num, i, true) = P.VU.elt<type##32_t>(rs2_num, i); \
+        break; \
+      case 0x88: \
+        P.VU.elt<type##64_t>(rd_num, i, true) = P.VU.elt<type##32_t>(rs2_num, i); \
+        break; \
+      default: \
+        break; \
+    } \
+  VI_LOOP_END 
+
 //
 // vector: vfp helper
 //

riscv/encoding.h

@@ -1391,6 +1391,18 @@
 #define MASK_VPOPC_M  0xfc0ff07f
 #define MATCH_VFIRST_M 0x4008a057
 #define MASK_VFIRST_M  0xfc0ff07f
+#define MATCH_VZEXT_VF2 0x48032057
+#define MASK_VZEXT_VF2  0xfc0ff07f
+#define MATCH_VSEXT_VF2 0x4803a057
+#define MASK_VSEXT_VF2  0xfc0ff07f
+#define MATCH_VZEXT_VF4 0x48022057
+#define MASK_VZEXT_VF4  0xfc0ff07f
+#define MATCH_VSEXT_VF4 0x4802a057
+#define MASK_VSEXT_VF4  0xfc0ff07f
+#define MATCH_VZEXT_VF8 0x48012057
+#define MASK_VZEXT_VF8  0xfc0ff07f
+#define MATCH_VSEXT_VF8 0x4801a057
+#define MASK_VSEXT_VF8  0xfc0ff07f
 #define MATCH_VMSBF_M 0x5000a057
 #define MASK_VMSBF_M  0xfc0ff07f
 #define MATCH_VMSOF_M 0x50012057
@@ -2443,6 +2455,12 @@ DECLARE_INSN(vasub_vv, MATCH_VASUB_VV, MASK_VASUB_VV)
 DECLARE_INSN(vmv_x_s, MATCH_VMV_X_S, MASK_VMV_X_S)
 DECLARE_INSN(vpopc_m, MATCH_VPOPC_M, MASK_VPOPC_M)
 DECLARE_INSN(vfirst_m, MATCH_VFIRST_M, MASK_VFIRST_M)
+DECLARE_INSN(vzext_vf2, MATCH_VZEXT_VF2, MASK_VZEXT_VF2)
+DECLARE_INSN(vsext_vf2, MATCH_VSEXT_VF2, MASK_VSEXT_VF2)
+DECLARE_INSN(vzext_vf4, MATCH_VZEXT_VF4, MASK_VZEXT_VF4)
+DECLARE_INSN(vsext_vf4, MATCH_VSEXT_VF4, MASK_VSEXT_VF4)
+DECLARE_INSN(vzext_vf8, MATCH_VZEXT_VF8, MASK_VZEXT_VF8)
+DECLARE_INSN(vsext_vf8, MATCH_VSEXT_VF8, MASK_VSEXT_VF8)
 DECLARE_INSN(vmsbf_m, MATCH_VMSBF_M, MASK_VMSBF_M)
 DECLARE_INSN(vmsof_m, MATCH_VMSOF_M, MASK_VMSOF_M)
 DECLARE_INSN(vmsif_m, MATCH_VMSIF_M, MASK_VMSIF_M)

riscv/insns/vsext_vf2.h

@@ -0,0 +1 @@
+VI_VV_EXT(2, int);

riscv/insns/vsext_vf4.h

@@ -0,0 +1 @@
+VI_VV_EXT(4, int);

riscv/insns/vsext_vf8.h

@@ -0,0 +1 @@
+VI_VV_EXT(8, int);

riscv/insns/vzext_vf2.h

@@ -0,0 +1 @@
+VI_VV_EXT(2, uint);

riscv/insns/vzext_vf4.h

@@ -0,0 +1 @@
+VI_VV_EXT(4, uint);

riscv/insns/vzext_vf8.h

@@ -0,0 +1 @@
+VI_VV_EXT(8, uint);

riscv/riscv.mk.in

@@ -442,6 +442,9 @@ riscv_insn_ext_v_alu_int = \
 	vsaddu_vx \
 	vsbc_vvm \
 	vsbc_vxm \
+	vsext_vf2 \
+	vsext_vf4 \
+	vsext_vf8 \
 	vslide1down_vx \
 	vslide1up_vx \
 	vslidedown_vi \
@@ -505,6 +508,9 @@ riscv_insn_ext_v_alu_int = \
 	vxor_vi \
 	vxor_vv \
 	vxor_vx \
+	vzext_vf2 \
+	vzext_vf4 \
+	vzext_vf8 \
 
 riscv_insn_ext_v_alu_fp = \
 	vfadd_vf \

spike_main/disasm.cc

@@ -919,6 +919,14 @@ disassembler_t::disassembler_t(int xlen)
   //VRXUNARY0
   DISASM_INSN("vmv.s.x", vmv_s_x, 0, {&vd, &xrs1});
 
+  //VXUNARY0
+  DISASM_INSN("vzext.vf2", vzext_vf2, 0, {&vd, &vs2, &opt, &vm});
+  DISASM_INSN("vsext.vf2", vsext_vf2, 0, {&vd, &vs2, &opt, &vm});
+  DISASM_INSN("vzext.vf4", vzext_vf4, 0, {&vd, &vs2, &opt, &vm});
+  DISASM_INSN("vsext.vf4", vsext_vf4, 0, {&vd, &vs2, &opt, &vm});
+  DISASM_INSN("vzext.vf8", vzext_vf8, 0, {&vd, &vs2, &opt, &vm});
+  DISASM_INSN("vsext.vf8", vsext_vf8, 0, {&vd, &vs2, &opt, &vm});
+
   //VMUNARY0
   DISASM_INSN("vmsbf.m", vmsbf_m, 0, {&vd, &vs2, &opt, &vm});
   DISASM_INSN("vmsof.m", vmsof_m, 0, {&vd, &vs2, &opt, &vm});