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Merge pull request #2077 from riscv-software-src/fix-2076
Prevent div-by-0 when executing Zvbdot instructions with VLEN=0
pull/2081/head
Andrew Waterman
11 months ago
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GitHub
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1 changed files with
1 additions and
1 deletions
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riscv/v_ext_macros.h
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@ -2088,11 +2088,11 @@ VI_VX_ULOOP({ \ |
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require_noover(insn.rd(), 1, insn.rs2(), P.VU.vflmul) |
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#define ZVBDOT_INIT(widen) \ |
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require_vector(true); \ |
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unsigned vd_eew = P.VU.vsew * (widen); \ |
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unsigned vd_emul = std::max(1U, unsigned((8 * vd_eew) / P.VU.VLEN)); \ |
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unsigned vs2 = insn.rs2() & ~7; \ |
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unsigned ci = (insn.rs2() & 7) * 8; \ |
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require_vector(true); \ |
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require(P.VU.vstart->read() == 0); \ |
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require(P.VU.vflmul == 1); \ |
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require(ci * vd_eew < P.VU.VLEN); \ |
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