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zve: correct the requirement for convension 

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
pull/2153/head
Chih-Min Chao 7 months ago
parent
d1e34d021f
commit
f364814542
12 changed files with 26 additions and 26 deletions
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  1. 10
      riscv/insns/vfncvt_f_x_w.h
  2. 10
      riscv/insns/vfncvt_f_xu_w.h
  3. 4
      riscv/insns/vfncvt_rtz_x_f_w.h
  4. 4
      riscv/insns/vfncvt_rtz_xu_f_w.h
  5. 4
      riscv/insns/vfncvt_x_f_w.h
  6. 4
      riscv/insns/vfncvt_xu_f_w.h
  7. 4
      riscv/insns/vfwcvt_f_x_v.h
  8. 4
      riscv/insns/vfwcvt_f_xu_v.h
  9. 2
      riscv/insns/vfwcvt_rtz_x_f_v.h
  10. 2
      riscv/insns/vfwcvt_rtz_xu_f_v.h
  11. 2
      riscv/insns/vfwcvt_x_f_v.h
  12. 2
      riscv/insns/vfwcvt_xu_f_v.h

10
riscv/insns/vfncvt_f_x_w.h
View File

@ -2,9 +2,9 @@
VI_NON_ALTFMT_INSN
VI_VFP_NCVT_INT_TO_FP(
{ vd = i32_to_f16(vs2); }, // BODY32
{ vd = i64_to_f32(vs2); }, // BODY64
{ require_extension(EXT_ZVFH); }, // CHECK32
{ require_extension('F'); }, // CHECK64
int // sign
{ vd = i32_to_f16(vs2); }, // BODY32
{ vd = i64_to_f32(vs2); }, // BODY64
{ require_extension(EXT_ZVFH); }, // CHECK32
{ require(p->get_isa().get_zvf()); }, // CHECK64
int // sign
)

10
riscv/insns/vfncvt_f_xu_w.h
View File

@ -2,9 +2,9 @@
VI_NON_ALTFMT_INSN
VI_VFP_NCVT_INT_TO_FP(
{ vd = ui32_to_f16(vs2); }, // BODY32
{ vd = ui64_to_f32(vs2); }, // BODY64
{ require_extension(EXT_ZVFH); }, // CHECK32
{ require_extension('F'); }, // CHECK64
uint // sign
{ vd = ui32_to_f16(vs2); }, // BODY32
{ vd = ui64_to_f32(vs2); }, // BODY64
{ require_extension(EXT_ZVFH); }, // CHECK32
{ require(p->get_isa().get_zvf()); }, // CHECK64
uint // sign
)

4
riscv/insns/vfncvt_rtz_x_f_w.h
View File

@ -6,7 +6,7 @@ VI_VFP_NCVT_FP_TO_INT(
{ vd = f32_to_i16(vs2, softfloat_round_minMag, true); }, // BODY32
{ vd = f64_to_i32(vs2, softfloat_round_minMag, true); }, // BODY64
{ require_zvfbfa_or_zvfh; }, // CHECK16
{ require(p->extension_enabled('F')); }, // CHECK32
{ require(p->extension_enabled('D')); }, // CHECK64
{ require(p->get_isa().get_zvf()); }, // CHECK32
{ require(p->get_isa().get_zvd()); }, // CHECK64
int // sign
)

4
riscv/insns/vfncvt_rtz_xu_f_w.h
View File

@ -6,7 +6,7 @@ VI_VFP_NCVT_FP_TO_INT(
{ vd = f32_to_ui16(vs2, softfloat_round_minMag, true); }, // BODY32
{ vd = f64_to_ui32(vs2, softfloat_round_minMag, true); }, // BODY64
{ require_zvfbfa_or_zvfh; }, // CHECK16
{ require(p->extension_enabled('F')); }, // CHECK32
{ require(p->extension_enabled('D')); }, // CHECK64
{ require(p->get_isa().get_zvf()); }, // CHECK32
{ require(p->get_isa().get_zvd()); }, // CHECK64
uint // sign
)

4
riscv/insns/vfncvt_x_f_w.h
View File

@ -6,7 +6,7 @@ VI_VFP_NCVT_FP_TO_INT(
{ vd = f32_to_i16(vs2, softfloat_roundingMode, true); }, // BODY32
{ vd = f64_to_i32(vs2, softfloat_roundingMode, true); }, // BODY64
{ require_zvfbfa_or_zvfh; }, // CHECK16
{ require(p->extension_enabled('F')); }, // CHECK32
{ require(p->extension_enabled('D')); }, // CHECK64
{ require(p->get_isa().get_zvf()); }, // CHECK32
{ require(p->get_isa().get_zvd()); }, // CHECK64
int // sign
)

4
riscv/insns/vfncvt_xu_f_w.h
View File

@ -6,7 +6,7 @@ VI_VFP_NCVT_FP_TO_INT(
{ vd = f32_to_ui16(vs2, softfloat_roundingMode, true); }, // BODY32
{ vd = f64_to_ui32(vs2, softfloat_roundingMode, true); }, // BODY64
{ require_zvfbfa_or_zvfh; }, // CHECK16
{ require(p->extension_enabled('F')); }, // CHECK32
{ require(p->extension_enabled('D')); }, // CHECK64
{ require(p->get_isa().get_zvf()); }, // CHECK32
{ require(p->get_isa().get_zvd()); }, // CHECK64
uint // sign
)

4
riscv/insns/vfwcvt_f_x_v.h
View File

@ -5,7 +5,7 @@ VI_VFP_WCVT_INT_TO_FP(
{ vd = i32_to_f32(vs2); }, // BODY16
{ vd = i32_to_f64(vs2); }, // BODY32
{ require_zvfbfa_or_zvfh; }, // CHECK8
{ require_extension('F'); }, // CHECK16
{ require_extension('D'); }, // CHECK32
{ require(p->get_isa().get_zvf()); }, // CHECK64
{ require(p->get_isa().get_zvd()); }, // CHECK64
int // sign
)

4
riscv/insns/vfwcvt_f_xu_v.h
View File

@ -5,7 +5,7 @@ VI_VFP_WCVT_INT_TO_FP(
{ vd = ui32_to_f32(vs2); }, // BODY16
{ vd = ui32_to_f64(vs2); }, // BODY32
{ require_zvfbfa_or_zvfh; }, // CHECK8
{ require_extension('F'); }, // CHECK16
{ require_extension('D'); }, // CHECK32
{ require(p->get_isa().get_zvf()); }, // CHECK32
{ require(p->get_isa().get_zvd()); }, // CHECK64
uint // sign
)

2
riscv/insns/vfwcvt_rtz_x_f_v.h
View File

@ -5,6 +5,6 @@ VI_VFP_WCVT_FP_TO_INT(
{ vd = f16_to_i32(vs2, softfloat_round_minMag, true); }, // BODY16
{ vd = f32_to_i64(vs2, softfloat_round_minMag, true); }, // BODY32
{ require_extension(EXT_ZVFH); }, // CHECK16
{ require_extension('F'); }, // CHECK32
{ require(p->get_isa().get_zvf()); }, // CHECK32
int // sign
)

2
riscv/insns/vfwcvt_rtz_xu_f_v.h
View File

@ -5,6 +5,6 @@ VI_VFP_WCVT_FP_TO_INT(
{ vd = f16_to_ui32(vs2, softfloat_round_minMag, true); }, // BODY16
{ vd = f32_to_ui64(vs2, softfloat_round_minMag, true); }, // BODY32
{ require_extension(EXT_ZVFH); }, // CHECK16
{ require_extension('F'); }, // CHECK32
{ require(p->get_isa().get_zvf()); }, // CHECK32
uint // sign
)

2
riscv/insns/vfwcvt_x_f_v.h
View File

@ -5,6 +5,6 @@ VI_VFP_WCVT_FP_TO_INT(
{ vd = f16_to_i32(vs2, softfloat_roundingMode, true); }, // BODY16
{ vd = f32_to_i64(vs2, softfloat_roundingMode, true); }, // BODY32
{ require_extension(EXT_ZVFH); }, // CHECK16
{ require_extension('F'); }, // CHECK32
{ require(p->get_isa().get_zvf()); }, // CHECK32
int // sign
)

2
riscv/insns/vfwcvt_xu_f_v.h
View File

@ -5,6 +5,6 @@ VI_VFP_WCVT_FP_TO_INT(
{ vd = f16_to_ui32(vs2, softfloat_roundingMode, true); }, // BODY16
{ vd = f32_to_ui64(vs2, softfloat_roundingMode, true); }, // BODY32
{ require_extension(EXT_ZVFH); }, // CHECK16
{ require_extension('F'); }, // CHECK32
{ require(p->get_isa().get_zvf()); }, // CHECK32
uint // sign
)

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