From f2a9fbeba2c66d5823cebbebd8de42b5e36f6f9c Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sat, 19 Feb 2022 01:19:20 -0800 Subject: [PATCH] Make comment more germane --- riscv/execute.cc | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/riscv/execute.cc b/riscv/execute.cc index 41a15b77..72ffa273 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -350,11 +350,7 @@ void processor_t::step(size_t n) state.minstret->bump(instret); - // By default, bump the MCYCLE register by the same delta. This models a - // machine where each instruction takes exactly one cycle to retire. In a - // cosimulation environment, the RTL might manually update MCYCLE - // separately. It should do that between the end of this step() and the - // start of the next one. + // Model a hart whose CPI is 1. state.mcycle->bump(instret); n -= instret;