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riscv-isa-sim
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WIP on FP encoding

fp-encoding
Andrew Waterman 9 years ago
parent
2c4a3aa729
commit
f2229668c3
19 changed files with 31 additions and 34 deletions
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  1. 21
      riscv/decode.h
  2. 2
      riscv/insns/c_fsd.h
  3. 2
      riscv/insns/c_fsdsp.h
  4. 2
      riscv/insns/c_fsw.h
  5. 2
      riscv/insns/c_fswsp.h
  6. 4
      riscv/insns/fmax_d.h
  7. 4
      riscv/insns/fmax_s.h
  8. 4
      riscv/insns/fmin_d.h
  9. 4
      riscv/insns/fmin_s.h
  10. 2
      riscv/insns/fmsub_d.h
  11. 2
      riscv/insns/fmsub_s.h
  12. 2
      riscv/insns/fmv_x_d.h
  13. 2
      riscv/insns/fmv_x_s.h
  14. 2
      riscv/insns/fnmadd_d.h
  15. 2
      riscv/insns/fnmadd_s.h
  16. 2
      riscv/insns/fnmsub_d.h
  17. 2
      riscv/insns/fnmsub_s.h
  18. 2
      riscv/insns/fsd.h
  19. 2
      riscv/insns/fsw.h

21
riscv/decode.h
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@ -18,16 +18,12 @@
#include "config.h"
#include "common.h"
#include "softfloat_types.h"
#include "specialize.h"
#include <cinttypes>
typedef int64_t sreg_t;
typedef uint64_t reg_t;
struct freg_t {
uint64_t v;
operator uint64_t() const { return v; }
};
const int NXPR = 32;
const int NFPR = 32;
const int NCSR = 4096;
@ -223,22 +219,23 @@ private:
#define invalid_pc(pc) ((pc) & 1)
/* Convenience wrappers to simplify softfloat code sequences */
#define isBoxedF32(r) (((r) & 0xffffffff00000000) == 0xffffffff00000000)
#define unboxF32(r) (isBoxedF32(r) ? (r) : defaultNaNF32UI)
#define unboxF64(r) (r)
struct freg_t { uint64_t v; };
inline float32_t f32(uint32_t v) { return { v }; }
inline float32_t f32(freg_t r) { return { uint32_t(r) }; }
inline float64_t f64(uint64_t v) { return { v }; }
inline float64_t f64(freg_t r) { return { uint64_t(r) }; }
inline float32_t f32(freg_t r) { return f32(unboxF32(r.v)); }
inline float64_t f64(freg_t r) { return f64(unboxF64(r.v)); }
inline freg_t freg(float32_t f) { return { ((decltype(freg_t::v))-1 << 32) | f.v }; }
inline freg_t freg(float64_t f) { return { f.v }; }
inline freg_t freg(freg_t f) { return f; }
#define F64_SIGN ((decltype(freg_t::v))1 << 63)
#define F32_SIGN ((decltype(freg_t::v))1 << 31)
#define isBoxedF32(r) (((r) & 0x7fffffff00000000) == 0x7fffffff00000000)
#define unboxF32(r) (isBoxedF32(r) ? (r) : defaultNaNF32UI)
#define unboxF64(r) (r)
#define fsgnj32(a, b, n, x) \
f32((unboxF32(a) & ~F32_SIGN) | ((((x) ? unboxF32(a) : (n) ? F32_SIGN : 0) ^ unboxF32(b)) & F32_SIGN))
f32((f32(a).v & ~F32_SIGN) | ((((x) ? f32(a).v : (n) ? F32_SIGN : 0) ^ f32(b).v) & F32_SIGN))
#define fsgnj64(a, b, n, x) \
f64((unboxF64(a) & ~F64_SIGN) | ((((x) ? unboxF64(a) : (n) ? F64_SIGN : 0) ^ unboxF64(b)) & F64_SIGN))
f64((f64(a).v & ~F64_SIGN) | ((((x) ? f64(a).v : (n) ? F64_SIGN : 0) ^ f64(b).v) & F64_SIGN))
#define validate_csr(which, write) ({ \
if (!STATE.serialized) return PC_SERIALIZE_BEFORE; \

2
riscv/insns/c_fsd.h
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@ -1,4 +1,4 @@
require_extension('C');
require_extension('D');
require_fp;
MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_FRS2S);
MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_FRS2S.v);

2
riscv/insns/c_fsdsp.h
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@ -1,4 +1,4 @@
require_extension('C');
require_extension('D');
require_fp;
MMU.store_uint64(RVC_SP + insn.rvc_sdsp_imm(), RVC_FRS2);
MMU.store_uint64(RVC_SP + insn.rvc_sdsp_imm(), RVC_FRS2.v);

2
riscv/insns/c_fsw.h
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@ -2,7 +2,7 @@ require_extension('C');
if (xlen == 32) {
require_extension('F');
require_fp;
MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S);
MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S.v);
} else { // c.sd
MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S);
}

2
riscv/insns/c_fswsp.h
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@ -2,7 +2,7 @@ require_extension('C');
if (xlen == 32) {
require_extension('F');
require_fp;
MMU.store_uint32(RVC_SP + insn.rvc_swsp_imm(), RVC_FRS2);
MMU.store_uint32(RVC_SP + insn.rvc_swsp_imm(), RVC_FRS2.v);
} else { // c.sdsp
MMU.store_uint64(RVC_SP + insn.rvc_sdsp_imm(), RVC_RS2);
}

4
riscv/insns/fmax_d.h
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@ -1,6 +1,6 @@
require_extension('D');
require_fp;
WRITE_FRD(f64_le_quiet(f64(FRS2), f64(FRS1)) || isNaNF64UI(uint64_t(FRS2)) ? FRS1 : FRS2);
if ((isNaNF64UI(uint64_t(FRS1)) && isNaNF64UI(uint64_t(FRS2))) || softfloat_exceptionFlags)
WRITE_FRD(f64_le_quiet(f64(FRS2), f64(FRS1)) || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2);
if ((isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v)) || softfloat_exceptionFlags)
WRITE_FRD(f64(defaultNaNF64UI));
set_fp_exceptions;

4
riscv/insns/fmax_s.h
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@ -1,6 +1,6 @@
require_extension('F');
require_fp;
WRITE_FRD(f32_le_quiet(f32(FRS2), f32(FRS1)) || isNaNF32UI(uint32_t(FRS2)) ? FRS1 : FRS2);
if ((isNaNF32UI(uint32_t(FRS1)) && isNaNF32UI(uint32_t(FRS2))) || softfloat_exceptionFlags)
WRITE_FRD(f32_le_quiet(f32(FRS2), f32(FRS1)) || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
if ((isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v)) || softfloat_exceptionFlags)
WRITE_FRD(f32(defaultNaNF32UI));
set_fp_exceptions;

4
riscv/insns/fmin_d.h
View File

@ -1,6 +1,6 @@
require_extension('D');
require_fp;
WRITE_FRD(f64_lt_quiet(f64(FRS1), f64(FRS2)) || isNaNF64UI(uint64_t(FRS2)) ? FRS1 : FRS2);
if ((isNaNF64UI(uint64_t(FRS1)) && isNaNF64UI(uint64_t(FRS2))) || softfloat_exceptionFlags)
WRITE_FRD(f64_lt_quiet(f64(FRS1), f64(FRS2)) || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2);
if ((isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v)) || softfloat_exceptionFlags)
WRITE_FRD(f64(defaultNaNF64UI));
set_fp_exceptions;

4
riscv/insns/fmin_s.h
View File

@ -1,6 +1,6 @@
require_extension('F');
require_fp;
WRITE_FRD(f32_lt_quiet(f32(FRS1), f32(FRS2)) || isNaNF32UI(uint32_t(FRS2)) ? FRS1 : FRS2);
if ((isNaNF32UI(uint32_t(FRS1)) && isNaNF32UI(uint32_t(FRS2))) || softfloat_exceptionFlags)
WRITE_FRD(f32_lt_quiet(f32(FRS1), f32(FRS2)) || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
if ((isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v)) || softfloat_exceptionFlags)
WRITE_FRD(f32(defaultNaNF32UI));
set_fp_exceptions;

2
riscv/insns/fmsub_d.h
View File

@ -1,5 +1,5 @@
require_extension('D');
require_fp;
softfloat_roundingMode = RM;
WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(FRS3 ^ (uint64_t)INT64_MIN)));
WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(f64(FRS3).v ^ F64_SIGN)));
set_fp_exceptions;

2
riscv/insns/fmsub_s.h
View File

@ -1,5 +1,5 @@
require_extension('F');
require_fp;
softfloat_roundingMode = RM;
WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(FRS3 ^ (uint32_t)INT32_MIN)));
WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(f32(FRS3).v ^ F32_SIGN)));
set_fp_exceptions;

2
riscv/insns/fmv_x_d.h
View File

@ -1,4 +1,4 @@
require_extension('D');
require_rv64;
require_fp;
WRITE_RD(FRS1);
WRITE_RD(FRS1.v);

2
riscv/insns/fmv_x_s.h
View File

@ -1,3 +1,3 @@
require_extension('F');
require_fp;
WRITE_RD(sext32(uint32_t(FRS1)));
WRITE_RD(sext32(FRS1.v));

2
riscv/insns/fnmadd_d.h
View File

@ -1,5 +1,5 @@
require_extension('D');
require_fp;
softfloat_roundingMode = RM;
WRITE_FRD(f64_mulAdd(f64(FRS1 ^ (uint64_t)INT64_MIN), f64(FRS2), f64(FRS3 ^ (uint64_t)INT64_MIN)));
WRITE_FRD(f64_mulAdd(f64(f64(FRS1).v ^ F64_SIGN), f64(FRS2), f64(f64(FRS3).v ^ F64_SIGN)));
set_fp_exceptions;

2
riscv/insns/fnmadd_s.h
View File

@ -1,5 +1,5 @@
require_extension('F');
require_fp;
softfloat_roundingMode = RM;
WRITE_FRD(f32_mulAdd(f32(FRS1 ^ (uint32_t)INT32_MIN), f32(FRS2), f32(FRS3 ^ (uint32_t)INT32_MIN)));
WRITE_FRD(f32_mulAdd(f32(f32(FRS1).v ^ F32_SIGN), f32(FRS2), f32(f32(FRS3).v ^ F32_SIGN)));
set_fp_exceptions;

2
riscv/insns/fnmsub_d.h
View File

@ -1,5 +1,5 @@
require_extension('D');
require_fp;
softfloat_roundingMode = RM;
WRITE_FRD(f64_mulAdd(f64(FRS1 ^ (uint64_t)INT64_MIN), f64(FRS2), f64(FRS3)));
WRITE_FRD(f64_mulAdd(f64(f64(FRS1).v ^ F64_SIGN), f64(FRS2), f64(FRS3)));
set_fp_exceptions;

2
riscv/insns/fnmsub_s.h
View File

@ -1,5 +1,5 @@
require_extension('F');
require_fp;
softfloat_roundingMode = RM;
WRITE_FRD(f32_mulAdd(f32(FRS1 ^ (uint32_t)INT32_MIN), f32(FRS2), f32(FRS3)));
WRITE_FRD(f32_mulAdd(f32(f32(FRS1).v ^ F32_SIGN), f32(FRS2), f32(FRS3)));
set_fp_exceptions;

2
riscv/insns/fsd.h
View File

@ -1,3 +1,3 @@
require_extension('D');
require_fp;
MMU.store_uint64(RS1 + insn.s_imm(), FRS2);
MMU.store_uint64(RS1 + insn.s_imm(), FRS2.v);

2
riscv/insns/fsw.h
View File

@ -1,3 +1,3 @@
require_extension('F');
require_fp;
MMU.store_uint32(RS1 + insn.s_imm(), FRS2);
MMU.store_uint32(RS1 + insn.s_imm(), FRS2.v);

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