Fix logging of FCSR and VCSR

It looks like `csrw fcsr` was intended to log writes to FFLAGS, FRM,
and FCSR, but only logged FCSR (because LOG_CSR() always used `which`
to record which CSR was written).

This changes it to log writes to FRM and FFLAGS, the two registers
which compose FCSR. There's no need to log FCSR since that is already
covered by the other two.

The logging of `csrw vcsr` was intended to log writes to VXSAT and
VXRM but instead would report a write to VCSR that only showed the
contents of VXRM.

riscv/processor.cc

@@ -960,7 +960,7 @@ void processor_t::set_csr(int which, reg_t val)
 {
 #if defined(RISCV_ENABLE_COMMITLOG)
 #define LOG_CSR(rd) \
-  STATE.log_reg_write[((which) << 4) | 4] = {get_csr(rd), 0};
+  STATE.log_reg_write[((rd) << 4) | 4] = {get_csr(rd), 0};
 #else
 #define LOG_CSR(rd)
 #endif
@@ -1021,7 +1021,6 @@ void processor_t::set_csr(int which, reg_t val)
     case CSR_FCSR:
       LOG_CSR(CSR_FFLAGS);
       LOG_CSR(CSR_FRM);
-      LOG_CSR(CSR_FCSR);
       break;
     case CSR_VCSR:
       LOG_CSR(CSR_VXSAT);