On misaligned fetch, set EPC to target, not branch itself

riscv/decode.h

@@ -155,11 +155,7 @@ private:
    ((x) & 0x3f) < 0x3f ? 6 : \
    8)
 
-#define set_pc(x) \
-  do { if ((x) & 3 /* For now... */) \
-         throw trap_instruction_address_misaligned(x); \
-       npc = sext_xprlen(x); \
-     } while(0)
+#define set_pc(x) (npc = sext_xprlen(x))
 
 #define validate_csr(which, write) ({ \
   unsigned my_priv = (STATE.sr & SR_S) ? 1 : 0; \

riscv/insns/jal.h

@@ -1,2 +1,3 @@
-WRITE_RD(npc);
+reg_t tmp = npc;
 set_pc(JUMP_TARGET);
+WRITE_RD(tmp);

riscv/insns/jalr.h

@@ -1,3 +1,3 @@
-reg_t temp = RS1;
-WRITE_RD(npc);
-set_pc((temp + insn.i_imm()) & ~1);
+reg_t tmp = npc;
+set_pc((RS1 + insn.i_imm()) & ~reg_t(1));
+WRITE_RD(tmp);

riscv/mmu.h

@@ -167,7 +167,9 @@ private:
     void* data = tlb_data[idx] + addr;
 
     if (unlikely(addr & (bytes-1)))
-      store ? throw trap_store_address_misaligned(addr) : throw trap_load_address_misaligned(addr);
+      store ? throw trap_store_address_misaligned(addr) :
+      fetch ? throw trap_instruction_address_misaligned(addr) :
+      throw trap_load_address_misaligned(addr);
 
     if (likely(tag == expected_tag))
       return data;