From e7f677b57fed9f753c16b48c255a7067424d6e69 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 24 May 2023 15:25:09 -0700 Subject: [PATCH] Prevent possibility of V=1 and PRV=M when entering debug mode --- riscv/processor.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/riscv/processor.cc b/riscv/processor.cc index 3d13f4e4..36452aac 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -764,6 +764,7 @@ void processor_t::enter_debug_mode(uint8_t cause) { state.debug_mode = true; state.dcsr->write_cause_and_prv(cause, state.prv, state.v); + set_virt(false); set_privilege(PRV_M); state.dpc->write(state.pc); state.pc = DEBUG_ROM_ENTRY;