Prevent possibility of V=1 and PRV=M when entering debug mode

riscv/processor.cc

@@ -764,6 +764,7 @@ void processor_t::enter_debug_mode(uint8_t cause)
 {
   state.debug_mode = true;
   state.dcsr->write_cause_and_prv(cause, state.prv, state.v);
+  set_virt(false);
   set_privilege(PRV_M);
   state.dpc->write(state.pc);
   state.pc = DEBUG_ROM_ENTRY;