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riscv-isa-sim
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Don't rely on definition of unratified bitmanip opcodes 

See https://github.com/riscv/riscv-opcodes/pull/401
pull/2208/head
Andrew Waterman 3 months ago
parent
26aab67907
commit
e532913fb3
13 changed files with 389 additions and 333 deletions
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  1. 8
      disasm/disasm.cc
  2. 674
      riscv/encoding.h
  3. 3
      riscv/insns/brev8.h
  4. 2
      riscv/insns/gorci.h
  5. 4
      riscv/insns/grevi.h
  6. 3
      riscv/insns/orc_b.h
  7. 4
      riscv/insns/rev8.h
  8. 4
      riscv/insns/rev8_rv32.h
  9. 2
      riscv/insns/shfli.h
  10. 2
      riscv/insns/unshfli.h
  11. 3
      riscv/insns/unzip.h
  12. 3
      riscv/insns/zip.h
  13. 10
      riscv/riscv.mk.in

8
disasm/disasm.cc
View File

@ -1132,8 +1132,8 @@ void disassembler_t::add_instructions(const isa_parser_t* isa, bool strict)
DEFINE_RTYPE(xnor);
DEFINE_R1TYPE(sext_b);
DEFINE_R1TYPE(sext_h);
add_insn(new disasm_insn_t("rev8", match_grevi | ((isa->get_max_xlen() - 8) << imm_shift), mask_grevi | mask_imm, {&xrd, &xrs1}));
add_insn(new disasm_insn_t("orc.b", match_gorci | (0x7 << imm_shift), mask_grevi | mask_imm, {&xrd, &xrs1}));
DEFINE_R1TYPE(rev8);
DEFINE_R1TYPE(orc_b);
add_insn(new disasm_insn_t("zext.h", (isa->get_max_xlen() == 32 ? match_pack : match_packw), mask_pack | mask_rs2, {&xrd, &xrs1}));
if (xlen_eq(64)) {
DEFINE_RTYPE(rorw);
@ -1163,8 +1163,8 @@ void disassembler_t::add_instructions(const isa_parser_t* isa, bool strict)
}
if (ext_enabled(EXT_ZBKB)) {
add_insn(new disasm_insn_t("brev8", match_grevi | (0x7 << imm_shift), mask_grevi | mask_imm, {&xrd, &xrs1})); // brev8
add_insn(new disasm_insn_t("rev8", match_grevi | ((isa->get_max_xlen() - 8) << imm_shift), mask_grevi | mask_imm, {&xrd, &xrs1}));
DEFINE_R1TYPE(brev8);
DEFINE_R1TYPE(rev8);
DEFINE_RTYPE(pack);
DEFINE_RTYPE(packh);
if (xlen_eq(64)) {

674
riscv/encoding.h
View File

@ -4,87 +4,95 @@
/*
* This file is auto-generated by running 'make' in
* https://github.com/riscv/riscv-opcodes (3deaa8c)
* https://github.com/riscv/riscv-opcodes (4644ba3)
*/
#ifndef RISCV_CSR_ENCODING_H
#define RISCV_CSR_ENCODING_H
#define MSTATUS_UIE 0x00000001
#define MSTATUS_SIE 0x00000002
#define MSTATUS_HIE 0x00000004
#define MSTATUS_MIE 0x00000008
#define MSTATUS_UPIE 0x00000010
#define MSTATUS_SPIE 0x00000020
#define MSTATUS_UBE 0x00000040
#define MSTATUS_MPIE 0x00000080
#define MSTATUS_SPP 0x00000100
#define MSTATUS_VS 0x00000600
#define MSTATUS_MPP 0x00001800
#define MSTATUS_FS 0x00006000
#define MSTATUS_XS 0x00018000
#define MSTATUS_MPRV 0x00020000
#define MSTATUS_SUM 0x00040000
#define MSTATUS_MXR 0x00080000
#define MSTATUS_TVM 0x00100000
#define MSTATUS_TW 0x00200000
#define MSTATUS_TSR 0x00400000
#define MSTATUS_SPELP 0x00800000
#define MSTATUS_SDT 0x01000000
#define MSTATUS32_SD 0x80000000
#define MSTATUS_UXL 0x0000000300000000
#define MSTATUS_SXL 0x0000000C00000000
#define MSTATUS_SBE 0x0000001000000000
#define MSTATUS_MBE 0x0000002000000000
#define MSTATUS_GVA 0x0000004000000000
#define MSTATUS_MPV 0x0000008000000000
#define MSTATUS_MPELP 0x0000020000000000
#define MSTATUS_MDT 0x0000040000000000
#define MSTATUS64_SD 0x8000000000000000
#ifdef __ASSEMBLY__
#define _RISCV_UL(x) x
#define _RISCV_ULL(x) x
#else
#define _RISCV_UL(x) x##UL
#define _RISCV_ULL(x) x##ULL
#endif
#define MSTATUS_UIE _RISCV_UL(0x00000001)
#define MSTATUS_SIE _RISCV_UL(0x00000002)
#define MSTATUS_HIE _RISCV_UL(0x00000004)
#define MSTATUS_MIE _RISCV_UL(0x00000008)
#define MSTATUS_UPIE _RISCV_UL(0x00000010)
#define MSTATUS_SPIE _RISCV_UL(0x00000020)
#define MSTATUS_UBE _RISCV_UL(0x00000040)
#define MSTATUS_MPIE _RISCV_UL(0x00000080)
#define MSTATUS_SPP _RISCV_UL(0x00000100)
#define MSTATUS_VS _RISCV_UL(0x00000600)
#define MSTATUS_MPP _RISCV_UL(0x00001800)
#define MSTATUS_FS _RISCV_UL(0x00006000)
#define MSTATUS_XS _RISCV_UL(0x00018000)
#define MSTATUS_MPRV _RISCV_UL(0x00020000)
#define MSTATUS_SUM _RISCV_UL(0x00040000)
#define MSTATUS_MXR _RISCV_UL(0x00080000)
#define MSTATUS_TVM _RISCV_UL(0x00100000)
#define MSTATUS_TW _RISCV_UL(0x00200000)
#define MSTATUS_TSR _RISCV_UL(0x00400000)
#define MSTATUS_SPELP _RISCV_UL(0x00800000)
#define MSTATUS_SDT _RISCV_UL(0x01000000)
#define MSTATUS32_SD _RISCV_UL(0x80000000)
#define MSTATUS_UXL _RISCV_ULL(0x0000000300000000)
#define MSTATUS_SXL _RISCV_ULL(0x0000000C00000000)
#define MSTATUS_SBE _RISCV_ULL(0x0000001000000000)
#define MSTATUS_MBE _RISCV_ULL(0x0000002000000000)
#define MSTATUS_GVA _RISCV_ULL(0x0000004000000000)
#define MSTATUS_MPV _RISCV_ULL(0x0000008000000000)
#define MSTATUS_MPELP _RISCV_ULL(0x0000020000000000)
#define MSTATUS_MDT _RISCV_ULL(0x0000040000000000)
#define MSTATUS64_SD _RISCV_ULL(0x8000000000000000)
#define MSTATUSH_SBE 0x00000010
#define MSTATUSH_MBE 0x00000020
#define MSTATUSH_GVA 0x00000040
#define MSTATUSH_MPV 0x00000080
#define MSTATUSH_MDT 0x00000400
#define MSTATUSH_SBE _RISCV_UL(0x00000010)
#define MSTATUSH_MBE _RISCV_UL(0x00000020)
#define MSTATUSH_GVA _RISCV_UL(0x00000040)
#define MSTATUSH_MPV _RISCV_UL(0x00000080)
#define MSTATUSH_MDT _RISCV_UL(0x00000400)
#define SSTATUS_UIE 0x00000001
#define SSTATUS_SIE 0x00000002
#define SSTATUS_UPIE 0x00000010
#define SSTATUS_SPIE 0x00000020
#define SSTATUS_UBE 0x00000040
#define SSTATUS_SPP 0x00000100
#define SSTATUS_VS 0x00000600
#define SSTATUS_FS 0x00006000
#define SSTATUS_XS 0x00018000
#define SSTATUS_SUM 0x00040000
#define SSTATUS_MXR 0x00080000
#define SSTATUS_SPELP 0x00800000
#define SSTATUS_SDT 0x01000000
#define SSTATUS32_SD 0x80000000
#define SSTATUS_UXL 0x0000000300000000
#define SSTATUS64_SD 0x8000000000000000
#define SSTATUS_UIE _RISCV_UL(0x00000001)
#define SSTATUS_SIE _RISCV_UL(0x00000002)
#define SSTATUS_UPIE _RISCV_UL(0x00000010)
#define SSTATUS_SPIE _RISCV_UL(0x00000020)
#define SSTATUS_UBE _RISCV_UL(0x00000040)
#define SSTATUS_SPP _RISCV_UL(0x00000100)
#define SSTATUS_VS _RISCV_UL(0x00000600)
#define SSTATUS_FS _RISCV_UL(0x00006000)
#define SSTATUS_XS _RISCV_UL(0x00018000)
#define SSTATUS_SUM _RISCV_UL(0x00040000)
#define SSTATUS_MXR _RISCV_UL(0x00080000)
#define SSTATUS_SPELP _RISCV_UL(0x00800000)
#define SSTATUS_SDT _RISCV_UL(0x01000000)
#define SSTATUS32_SD _RISCV_UL(0x80000000)
#define SSTATUS_UXL _RISCV_ULL(0x0000000300000000)
#define SSTATUS64_SD _RISCV_ULL(0x8000000000000000)
#define HSTATUS_VSBE 0x00000020
#define HSTATUS_GVA 0x00000040
#define HSTATUS_SPV 0x00000080
#define HSTATUS_SPVP 0x00000100
#define HSTATUS_HU 0x00000200
#define HSTATUS_VGEIN 0x0003f000
#define HSTATUS_VTVM 0x00100000
#define HSTATUS_VTW 0x00200000
#define HSTATUS_VTSR 0x00400000
#define HSTATUS_HUKTE 0x01000000
#define HSTATUS_VSXL 0x0000000300000000
#define HSTATUS_HUPMM 0x0003000000000000
#define HSTATUS_VSBE _RISCV_UL(0x00000020)
#define HSTATUS_GVA _RISCV_UL(0x00000040)
#define HSTATUS_SPV _RISCV_UL(0x00000080)
#define HSTATUS_SPVP _RISCV_UL(0x00000100)
#define HSTATUS_HU _RISCV_UL(0x00000200)
#define HSTATUS_VGEIN _RISCV_UL(0x0003f000)
#define HSTATUS_VTVM _RISCV_UL(0x00100000)
#define HSTATUS_VTW _RISCV_UL(0x00200000)
#define HSTATUS_VTSR _RISCV_UL(0x00400000)
#define HSTATUS_HUKTE _RISCV_UL(0x01000000)
#define HSTATUS_VSXL _RISCV_ULL(0x0000000300000000)
#define HSTATUS_HUPMM _RISCV_ULL(0x0003000000000000)
#define USTATUS_UIE 0x00000001
#define USTATUS_UPIE 0x00000010
#define USTATUS_UIE _RISCV_UL(0x00000001)
#define USTATUS_UPIE _RISCV_UL(0x00000010)
#define MNSTATUS_NMIE 0x00000008
#define MNSTATUS_MNPV 0x00000080
#define MNSTATUS_MNPELP 0x00000200
#define MNSTATUS_MNPP 0x00001800
#define MNSTATUS_NMIE _RISCV_UL(0x00000008)
#define MNSTATUS_MNPV _RISCV_UL(0x00000080)
#define MNSTATUS_MNPELP _RISCV_UL(0x00000200)
#define MNSTATUS_MNPP _RISCV_UL(0x00001800)
#define DCSR_XDEBUGVER (15U<<28)
#define DCSR_EXTCAUSE (7<<24)
@ -116,9 +124,9 @@
#define DCSR_EXTCAUSE_CRITERR 0
#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4))
#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5))
#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
#define MCONTROL_TYPE(xlen) (_RISCV_ULL(0xf)<<((xlen)-4))
#define MCONTROL_DMODE(xlen) (_RISCV_ULL(1)<<((xlen)-5))
#define MCONTROL_MASKMAX(xlen) (_RISCV_ULL(0x3f)<<((xlen)-11))
#define MCONTROL_SELECT (1<<19)
#define MCONTROL_TIMING (1<<18)
@ -163,8 +171,8 @@
#define MIP_MEIP (1 << IRQ_M_EXT)
#define MIP_SGEIP (1 << IRQ_S_GEXT)
#define MIP_LCOFIP (1 << IRQ_LCOF)
#define MIP_RAS_LOW_PRIO (1ULL << IRQ_RAS_LOW_PRIO)
#define MIP_RAS_HIGH_PRIO (1ULL << IRQ_RAS_HIGH_PRIO)
#define MIP_RAS_LOW_PRIO (_RISCV_ULL(1) << IRQ_RAS_LOW_PRIO)
#define MIP_RAS_HIGH_PRIO (_RISCV_ULL(1) << IRQ_RAS_HIGH_PRIO)
#define MIP_S_MASK (MIP_SSIP | MIP_STIP | MIP_SEIP)
#define MIP_VS_MASK (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
@ -175,61 +183,61 @@
#define SIP_SSIP MIP_SSIP
#define SIP_STIP MIP_STIP
#define MENVCFG_FIOM 0x00000001
#define MENVCFG_LPE 0x00000004
#define MENVCFG_SSE 0x00000008
#define MENVCFG_CBIE 0x00000030
#define MENVCFG_CBCFE 0x00000040
#define MENVCFG_CBZE 0x00000080
#define MENVCFG_PMM 0x0000000300000000
#define MENVCFG_DTE 0x0800000000000000
#define MENVCFG_CDE 0x1000000000000000
#define MENVCFG_ADUE 0x2000000000000000
#define MENVCFG_PBMTE 0x4000000000000000
#define MENVCFG_STCE 0x8000000000000000
#define MENVCFG_FIOM _RISCV_UL(0x00000001)
#define MENVCFG_LPE _RISCV_UL(0x00000004)
#define MENVCFG_SSE _RISCV_UL(0x00000008)
#define MENVCFG_CBIE _RISCV_UL(0x00000030)
#define MENVCFG_CBCFE _RISCV_UL(0x00000040)
#define MENVCFG_CBZE _RISCV_UL(0x00000080)
#define MENVCFG_PMM _RISCV_ULL(0x0000000300000000)
#define MENVCFG_DTE _RISCV_ULL(0x0800000000000000)
#define MENVCFG_CDE _RISCV_ULL(0x1000000000000000)
#define MENVCFG_ADUE _RISCV_ULL(0x2000000000000000)
#define MENVCFG_PBMTE _RISCV_ULL(0x4000000000000000)
#define MENVCFG_STCE _RISCV_ULL(0x8000000000000000)
#define MENVCFGH_DTE 0x08000000
#define MENVCFGH_CDE 0x10000000
#define MENVCFGH_ADUE 0x20000000
#define MENVCFGH_PBMTE 0x40000000
#define MENVCFGH_STCE 0x80000000
#define MENVCFGH_DTE _RISCV_UL(0x08000000)
#define MENVCFGH_CDE _RISCV_UL(0x10000000)
#define MENVCFGH_ADUE _RISCV_UL(0x20000000)
#define MENVCFGH_PBMTE _RISCV_UL(0x40000000)
#define MENVCFGH_STCE _RISCV_UL(0x80000000)
#define MSTATEEN0_CS 0x00000001
#define MSTATEEN0_FCSR 0x00000002
#define MSTATEEN0_JVT 0x00000004
#define MSTATEEN0_CTR 0x0040000000000000
#define MSTATEEN0_PRIV114 0x0080000000000000
#define MSTATEEN0_PRIV113 0x0100000000000000
#define MSTATEEN0_HCONTEXT 0x0200000000000000
#define MSTATEEN0_IMSIC 0x0400000000000000
#define MSTATEEN0_AIA 0x0800000000000000
#define MSTATEEN0_CSRIND 0x1000000000000000
#define MSTATEEN0_HENVCFG 0x4000000000000000
#define MSTATEEN_HSTATEEN 0x8000000000000000
#define MSTATEEN0_CS _RISCV_UL(0x00000001)
#define MSTATEEN0_FCSR _RISCV_UL(0x00000002)
#define MSTATEEN0_JVT _RISCV_UL(0x00000004)
#define MSTATEEN0_CTR _RISCV_ULL(0x0040000000000000)
#define MSTATEEN0_PRIV114 _RISCV_ULL(0x0080000000000000)
#define MSTATEEN0_PRIV113 _RISCV_ULL(0x0100000000000000)
#define MSTATEEN0_HCONTEXT _RISCV_ULL(0x0200000000000000)
#define MSTATEEN0_IMSIC _RISCV_ULL(0x0400000000000000)
#define MSTATEEN0_AIA _RISCV_ULL(0x0800000000000000)
#define MSTATEEN0_CSRIND _RISCV_ULL(0x1000000000000000)
#define MSTATEEN0_HENVCFG _RISCV_ULL(0x4000000000000000)
#define MSTATEEN_HSTATEEN _RISCV_ULL(0x8000000000000000)
#define MSTATEEN0H_CTR 0x00400000
#define MSTATEEN0H_PRIV114 0x00800000
#define MSTATEEN0H_PRIV113 0x01000000
#define MSTATEEN0H_HCONTEXT 0x02000000
#define MSTATEEN0H_IMSIC 0x04000000
#define MSTATEEN0H_AIA 0x08000000
#define MSTATEEN0H_CSRIND 0x10000000
#define MSTATEEN0H_HENVCFG 0x40000000
#define MSTATEENH_HSTATEEN 0x80000000
#define MSTATEEN0H_CTR _RISCV_UL(0x00400000)
#define MSTATEEN0H_PRIV114 _RISCV_UL(0x00800000)
#define MSTATEEN0H_PRIV113 _RISCV_UL(0x01000000)
#define MSTATEEN0H_HCONTEXT _RISCV_UL(0x02000000)
#define MSTATEEN0H_IMSIC _RISCV_UL(0x04000000)
#define MSTATEEN0H_AIA _RISCV_UL(0x08000000)
#define MSTATEEN0H_CSRIND _RISCV_UL(0x10000000)
#define MSTATEEN0H_HENVCFG _RISCV_UL(0x40000000)
#define MSTATEENH_HSTATEEN _RISCV_UL(0x80000000)
#define MHPMEVENT_VUINH 0x0400000000000000
#define MHPMEVENT_VSINH 0x0800000000000000
#define MHPMEVENT_UINH 0x1000000000000000
#define MHPMEVENT_SINH 0x2000000000000000
#define MHPMEVENT_MINH 0x4000000000000000
#define MHPMEVENT_OF 0x8000000000000000
#define MHPMEVENT_VUINH _RISCV_ULL(0x0400000000000000)
#define MHPMEVENT_VSINH _RISCV_ULL(0x0800000000000000)
#define MHPMEVENT_UINH _RISCV_ULL(0x1000000000000000)
#define MHPMEVENT_SINH _RISCV_ULL(0x2000000000000000)
#define MHPMEVENT_MINH _RISCV_ULL(0x4000000000000000)
#define MHPMEVENT_OF _RISCV_ULL(0x8000000000000000)
#define MHPMEVENTH_VUINH 0x04000000
#define MHPMEVENTH_VSINH 0x08000000
#define MHPMEVENTH_UINH 0x10000000
#define MHPMEVENTH_SINH 0x20000000
#define MHPMEVENTH_MINH 0x40000000
#define MHPMEVENTH_OF 0x80000000
#define MHPMEVENTH_VUINH _RISCV_UL(0x04000000)
#define MHPMEVENTH_VSINH _RISCV_UL(0x08000000)
#define MHPMEVENTH_UINH _RISCV_UL(0x10000000)
#define MHPMEVENTH_SINH _RISCV_UL(0x20000000)
#define MHPMEVENTH_MINH _RISCV_UL(0x40000000)
#define MHPMEVENTH_OF _RISCV_UL(0x80000000)
#define MCOUNTEREN_CY_SHIFT 0
#define MCOUNTEREN_TIME_SHIFT 1
@ -242,100 +250,100 @@
#define MCOUNTINHIBIT_CY MCOUNTEREN_CY
#define MCOUNTINHIBIT_IR MCOUNTEREN_IR
#define HENVCFG_FIOM 0x00000001
#define HENVCFG_LPE 0x00000004
#define HENVCFG_SSE 0x00000008
#define HENVCFG_CBIE 0x00000030
#define HENVCFG_CBCFE 0x00000040
#define HENVCFG_CBZE 0x00000080
#define HENVCFG_PMM 0x0000000300000000
#define HENVCFG_DTE 0x0800000000000000
#define HENVCFG_ADUE 0x2000000000000000
#define HENVCFG_PBMTE 0x4000000000000000
#define HENVCFG_STCE 0x8000000000000000
#define HENVCFG_FIOM _RISCV_UL(0x00000001)
#define HENVCFG_LPE _RISCV_UL(0x00000004)
#define HENVCFG_SSE _RISCV_UL(0x00000008)
#define HENVCFG_CBIE _RISCV_UL(0x00000030)
#define HENVCFG_CBCFE _RISCV_UL(0x00000040)
#define HENVCFG_CBZE _RISCV_UL(0x00000080)
#define HENVCFG_PMM _RISCV_ULL(0x0000000300000000)
#define HENVCFG_DTE _RISCV_ULL(0x0800000000000000)
#define HENVCFG_ADUE _RISCV_ULL(0x2000000000000000)
#define HENVCFG_PBMTE _RISCV_ULL(0x4000000000000000)
#define HENVCFG_STCE _RISCV_ULL(0x8000000000000000)
#define HENVCFGH_DTE 0x08000000
#define HENVCFGH_ADUE 0x20000000
#define HENVCFGH_PBMTE 0x40000000
#define HENVCFGH_STCE 0x80000000
#define HENVCFGH_DTE _RISCV_UL(0x08000000)
#define HENVCFGH_ADUE _RISCV_UL(0x20000000)
#define HENVCFGH_PBMTE _RISCV_UL(0x40000000)
#define HENVCFGH_STCE _RISCV_UL(0x80000000)
#define SISELECT_SMCDELEG_START 0x40
#define SISELECT_SMCDELEG_UNUSED 0x41
#define SISELECT_SMCDELEG_INSTRET 0x42
#define SISELECT_SMCDELEG_INSTRETCFG 0x42
#define SISELECT_SMCDELEG_START _RISCV_UL(0x40)
#define SISELECT_SMCDELEG_UNUSED _RISCV_UL(0x41)
#define SISELECT_SMCDELEG_INSTRET _RISCV_UL(0x42)
#define SISELECT_SMCDELEG_INSTRETCFG _RISCV_UL(0x42)
/*
* ?iselect values for hpmcounters4..31 and hpmevent4..31
* can easily computed, and were elided for brevity.
*/
#define SISELECT_SMCDELEG_HPMCOUNTER_3 0x43
#define SISELECT_SMCDELEG_HPMEVENT_3 0x43
#define SISELECT_SMCDELEG_END 0x5f
#define SISELECT_SMCDELEG_HPMCOUNTER_3 _RISCV_UL(0x43)
#define SISELECT_SMCDELEG_HPMEVENT_3 _RISCV_UL(0x43)
#define SISELECT_SMCDELEG_END _RISCV_UL(0x5f)
#define MISELECT_IPRIO 0x30
#define MISELECT_IPRIO_TOP 0x3f
#define MISELECT_IMSIC 0x70
#define MISELECT_IMSIC_TOP 0xff
#define MISELECT_IPRIO _RISCV_UL(0x30)
#define MISELECT_IPRIO_TOP _RISCV_UL(0x3f)
#define MISELECT_IMSIC _RISCV_UL(0x70)
#define MISELECT_IMSIC_TOP _RISCV_UL(0xff)
#define SISELECT_IPRIO 0x30
#define SISELECT_IPRIO_TOP 0x3f
#define SISELECT_IMSIC 0x70
#define SISELECT_IMSIC_TOP 0xff
#define SISELECT_IPRIO _RISCV_UL(0x30)
#define SISELECT_IPRIO_TOP _RISCV_UL(0x3f)
#define SISELECT_IMSIC _RISCV_UL(0x70)
#define SISELECT_IMSIC_TOP _RISCV_UL(0xff)
#define VSISELECT_IMSIC 0x70
#define VSISELECT_IMSIC_TOP 0xff
#define VSISELECT_IMSIC _RISCV_UL(0x70)
#define VSISELECT_IMSIC_TOP _RISCV_UL(0xff)
#define HSTATEEN0_CS 0x00000001
#define HSTATEEN0_FCSR 0x00000002
#define HSTATEEN0_JVT 0x00000004
#define HSTATEEN0_CTR 0x0040000000000000
#define HSTATEEN0_SCONTEXT 0x0200000000000000
#define HSTATEEN0_IMSIC 0x0400000000000000
#define HSTATEEN0_AIA 0x0800000000000000
#define HSTATEEN0_CSRIND 0x1000000000000000
#define HSTATEEN0_SENVCFG 0x4000000000000000
#define HSTATEEN_SSTATEEN 0x8000000000000000
#define HSTATEEN0_CS _RISCV_UL(0x00000001)
#define HSTATEEN0_FCSR _RISCV_UL(0x00000002)
#define HSTATEEN0_JVT _RISCV_UL(0x00000004)
#define HSTATEEN0_CTR _RISCV_ULL(0x0040000000000000)
#define HSTATEEN0_SCONTEXT _RISCV_ULL(0x0200000000000000)
#define HSTATEEN0_IMSIC _RISCV_ULL(0x0400000000000000)
#define HSTATEEN0_AIA _RISCV_ULL(0x0800000000000000)
#define HSTATEEN0_CSRIND _RISCV_ULL(0x1000000000000000)
#define HSTATEEN0_SENVCFG _RISCV_ULL(0x4000000000000000)
#define HSTATEEN_SSTATEEN _RISCV_ULL(0x8000000000000000)
#define HSTATEEN0H_CTR 0x00400000
#define HSTATEEN0H_SCONTEXT 0x02000000
#define HSTATEEN0H_IMSIC 0x04000000
#define HSTATEEN0H_AIA 0x08000000
#define HSTATEEN0H_CSRIND 0x10000000
#define HSTATEEN0H_SENVCFG 0x40000000
#define HSTATEENH_SSTATEEN 0x80000000
#define HSTATEEN0H_CTR _RISCV_UL(0x00400000)
#define HSTATEEN0H_SCONTEXT _RISCV_UL(0x02000000)
#define HSTATEEN0H_IMSIC _RISCV_UL(0x04000000)
#define HSTATEEN0H_AIA _RISCV_UL(0x08000000)
#define HSTATEEN0H_CSRIND _RISCV_UL(0x10000000)
#define HSTATEEN0H_SENVCFG _RISCV_UL(0x40000000)
#define HSTATEENH_SSTATEEN _RISCV_UL(0x80000000)
#define SENVCFG_FIOM 0x00000001
#define SENVCFG_LPE 0x00000004
#define SENVCFG_SSE 0x00000008
#define SENVCFG_CBIE 0x00000030
#define SENVCFG_CBCFE 0x00000040
#define SENVCFG_CBZE 0x00000080
#define SENVCFG_UKTE 0x00000100
#define SENVCFG_PMM 0x0000000300000000
#define SENVCFG_FIOM _RISCV_UL(0x00000001)
#define SENVCFG_LPE _RISCV_UL(0x00000004)
#define SENVCFG_SSE _RISCV_UL(0x00000008)
#define SENVCFG_CBIE _RISCV_UL(0x00000030)
#define SENVCFG_CBCFE _RISCV_UL(0x00000040)
#define SENVCFG_CBZE _RISCV_UL(0x00000080)
#define SENVCFG_UKTE _RISCV_UL(0x00000100)
#define SENVCFG_PMM _RISCV_ULL(0x0000000300000000)
#define SSTATEEN0_CS 0x00000001
#define SSTATEEN0_FCSR 0x00000002
#define SSTATEEN0_JVT 0x00000004
#define SSTATEEN0_CS _RISCV_UL(0x00000001)
#define SSTATEEN0_FCSR _RISCV_UL(0x00000002)
#define SSTATEEN0_JVT _RISCV_UL(0x00000004)
#define MSECCFG_MML 0x00000001
#define MSECCFG_MMWP 0x00000002
#define MSECCFG_RLB 0x00000004
#define MSECCFG_USEED 0x00000100
#define MSECCFG_SSEED 0x00000200
#define MSECCFG_MLPE 0x00000400
#define MSECCFG_PMM 0x0000000300000000
#define MSECCFG_MML _RISCV_UL(0x00000001)
#define MSECCFG_MMWP _RISCV_UL(0x00000002)
#define MSECCFG_RLB _RISCV_UL(0x00000004)
#define MSECCFG_USEED _RISCV_UL(0x00000100)
#define MSECCFG_SSEED _RISCV_UL(0x00000200)
#define MSECCFG_MLPE _RISCV_UL(0x00000400)
#define MSECCFG_PMM _RISCV_ULL(0x0000000300000000)
/* jvt fields */
#define JVT_MODE 0x3F
#define JVT_MODE _RISCV_UL(0x3F)
#define JVT_BASE (~0x3F)
#define HVICTL_VTI 0x40000000
#define HVICTL_IID 0x003F0000
#define HVICTL_DPR 0x00000200
#define HVICTL_IPRIOM 0x00000100
#define HVICTL_IPRIO 0x000000FF
#define HVICTL_VTI _RISCV_UL(0x40000000)
#define HVICTL_IID _RISCV_UL(0x003F0000)
#define HVICTL_DPR _RISCV_UL(0x00000200)
#define HVICTL_IPRIOM _RISCV_UL(0x00000100)
#define HVICTL_IPRIO _RISCV_UL(0x000000FF)
#define MTOPI_IID 0x0FFF0000
#define MTOPI_IPRIO 0x000000FF
#define MTOPI_IID _RISCV_UL(0x0FFF0000)
#define MTOPI_IPRIO _RISCV_UL(0x000000FF)
#define PRV_U 0
#define PRV_S 1
@ -343,12 +351,12 @@
#define PRV_HS (PRV_S + 1)
#define SATP32_MODE 0x80000000
#define SATP32_ASID 0x7FC00000
#define SATP32_PPN 0x003FFFFF
#define SATP64_MODE 0xF000000000000000
#define SATP64_ASID 0x0FFFF00000000000
#define SATP64_PPN 0x00000FFFFFFFFFFF
#define SATP32_MODE _RISCV_UL(0x80000000)
#define SATP32_ASID _RISCV_UL(0x7FC00000)
#define SATP32_PPN _RISCV_UL(0x003FFFFF)
#define SATP64_MODE _RISCV_ULL(0xF000000000000000)
#define SATP64_ASID _RISCV_ULL(0x0FFFF00000000000)
#define SATP64_PPN _RISCV_ULL(0x00000FFFFFFFFFFF)
#define SATP_MODE_OFF 0
#define SATP_MODE_SV32 1
@ -357,13 +365,13 @@
#define SATP_MODE_SV57 10
#define SATP_MODE_SV64 11
#define HGATP32_MODE 0x80000000
#define HGATP32_VMID 0x1FC00000
#define HGATP32_PPN 0x003FFFFF
#define HGATP32_MODE _RISCV_UL(0x80000000)
#define HGATP32_VMID _RISCV_UL(0x1FC00000)
#define HGATP32_PPN _RISCV_UL(0x003FFFFF)
#define HGATP64_MODE 0xF000000000000000
#define HGATP64_VMID 0x03FFF00000000000
#define HGATP64_PPN 0x00000FFFFFFFFFFF
#define HGATP64_MODE _RISCV_ULL(0xF000000000000000)
#define HGATP64_VMID _RISCV_ULL(0x03FFF00000000000)
#define HGATP64_PPN _RISCV_ULL(0x00000FFFFFFFFFFF)
#define HGATP_MODE_OFF 0
#define HGATP_MODE_SV32X4 1
@ -371,101 +379,101 @@
#define HGATP_MODE_SV48X4 9
#define HGATP_MODE_SV57X4 10
#define PMP_R 0x01
#define PMP_W 0x02
#define PMP_X 0x04
#define PMP_A 0x18
#define PMP_MT 0x60
#define PMP_L 0x80
#define PMP_R _RISCV_UL(0x01)
#define PMP_W _RISCV_UL(0x02)
#define PMP_X _RISCV_UL(0x04)
#define PMP_A _RISCV_UL(0x18)
#define PMP_MT _RISCV_UL(0x60)
#define PMP_L _RISCV_UL(0x80)
#define PMP_SHIFT 2
#define PMP_TOR 0x08
#define PMP_NA4 0x10
#define PMP_NAPOT 0x18
#define PMP_TOR _RISCV_UL(0x08)
#define PMP_NA4 _RISCV_UL(0x10)
#define PMP_NAPOT _RISCV_UL(0x18)
#define SPMP_U 0x100
#define SPMP_SHARED 0x200
#define SPMP_U _RISCV_UL(0x100)
#define SPMP_SHARED _RISCV_UL(0x200)
#define MCTRCTL_U 0x0000000000000001
#define MCTRCTL_S 0x0000000000000002
#define MCTRCTL_M 0x0000000000000004
#define MCTRCTL_RASEMU 0x0000000000000080
#define MCTRCTL_STE 0x0000000000000100
#define MCTRCTL_MTE 0x0000000000000200
#define MCTRCTL_BPFRZ 0x0000000000000800
#define MCTRCTL_LCOFIFRZ 0x0000000000001000
#define MCTRCTL_EXCINH 0x0000000200000000
#define MCTRCTL_INTRINH 0x0000000400000000
#define MCTRCTL_TRETINH 0x0000000800000000
#define MCTRCTL_NTBREN 0x0000001000000000
#define MCTRCTL_TKBRINH 0x0000002000000000
#define MCTRCTL_INDCALLINH 0x0000010000000000
#define MCTRCTL_DIRCALLINH 0x0000020000000000
#define MCTRCTL_INDJMPINH 0x0000040000000000
#define MCTRCTL_DIRJMPINH 0x0000080000000000
#define MCTRCTL_CORSWAPINH 0x0000100000000000
#define MCTRCTL_RETINH 0x0000200000000000
#define MCTRCTL_INDLJMPINH 0x0000400000000000
#define MCTRCTL_DIRLJMPINH 0x0000800000000000
#define MCTRCTL_CUSTOM 0xF000000000000000
#define MCTRCTL_U _RISCV_ULL(0x0000000000000001)
#define MCTRCTL_S _RISCV_ULL(0x0000000000000002)
#define MCTRCTL_M _RISCV_ULL(0x0000000000000004)
#define MCTRCTL_RASEMU _RISCV_ULL(0x0000000000000080)
#define MCTRCTL_STE _RISCV_ULL(0x0000000000000100)
#define MCTRCTL_MTE _RISCV_ULL(0x0000000000000200)
#define MCTRCTL_BPFRZ _RISCV_ULL(0x0000000000000800)
#define MCTRCTL_LCOFIFRZ _RISCV_ULL(0x0000000000001000)
#define MCTRCTL_EXCINH _RISCV_ULL(0x0000000200000000)
#define MCTRCTL_INTRINH _RISCV_ULL(0x0000000400000000)
#define MCTRCTL_TRETINH _RISCV_ULL(0x0000000800000000)
#define MCTRCTL_NTBREN _RISCV_ULL(0x0000001000000000)
#define MCTRCTL_TKBRINH _RISCV_ULL(0x0000002000000000)
#define MCTRCTL_INDCALLINH _RISCV_ULL(0x0000010000000000)
#define MCTRCTL_DIRCALLINH _RISCV_ULL(0x0000020000000000)
#define MCTRCTL_INDJMPINH _RISCV_ULL(0x0000040000000000)
#define MCTRCTL_DIRJMPINH _RISCV_ULL(0x0000080000000000)
#define MCTRCTL_CORSWAPINH _RISCV_ULL(0x0000100000000000)
#define MCTRCTL_RETINH _RISCV_ULL(0x0000200000000000)
#define MCTRCTL_INDLJMPINH _RISCV_ULL(0x0000400000000000)
#define MCTRCTL_DIRLJMPINH _RISCV_ULL(0x0000800000000000)
#define MCTRCTL_CUSTOM _RISCV_ULL(0xF000000000000000)
#define SCTRCTL_U 0x0000000000000001
#define SCTRCTL_S 0x0000000000000002
#define SCTRCTL_RASEMU 0x0000000000000080
#define SCTRCTL_STE 0x0000000000000100
#define SCTRCTL_BPFRZ 0x0000000000000800
#define SCTRCTL_LCOFIFRZ 0x0000000000001000
#define SCTRCTL_EXCINH 0x0000000200000000
#define SCTRCTL_INTRINH 0x0000000400000000
#define SCTRCTL_TRETINH 0x0000000800000000
#define SCTRCTL_NTBREN 0x0000001000000000
#define SCTRCTL_TKBRINH 0x0000002000000000
#define SCTRCTL_INDCALLINH 0x0000010000000000
#define SCTRCTL_DIRCALLINH 0x0000020000000000
#define SCTRCTL_INDJMPINH 0x0000040000000000
#define SCTRCTL_DIRJMPINH 0x0000080000000000
#define SCTRCTL_CORSWAPINH 0x0000100000000000
#define SCTRCTL_RETINH 0x0000200000000000
#define SCTRCTL_INDLJMPINH 0x0000400000000000
#define SCTRCTL_DIRLJMPINH 0x0000800000000000
#define SCTRCTL_U _RISCV_ULL(0x0000000000000001)
#define SCTRCTL_S _RISCV_ULL(0x0000000000000002)
#define SCTRCTL_RASEMU _RISCV_ULL(0x0000000000000080)
#define SCTRCTL_STE _RISCV_ULL(0x0000000000000100)
#define SCTRCTL_BPFRZ _RISCV_ULL(0x0000000000000800)
#define SCTRCTL_LCOFIFRZ _RISCV_ULL(0x0000000000001000)
#define SCTRCTL_EXCINH _RISCV_ULL(0x0000000200000000)
#define SCTRCTL_INTRINH _RISCV_ULL(0x0000000400000000)
#define SCTRCTL_TRETINH _RISCV_ULL(0x0000000800000000)
#define SCTRCTL_NTBREN _RISCV_ULL(0x0000001000000000)
#define SCTRCTL_TKBRINH _RISCV_ULL(0x0000002000000000)
#define SCTRCTL_INDCALLINH _RISCV_ULL(0x0000010000000000)
#define SCTRCTL_DIRCALLINH _RISCV_ULL(0x0000020000000000)
#define SCTRCTL_INDJMPINH _RISCV_ULL(0x0000040000000000)
#define SCTRCTL_DIRJMPINH _RISCV_ULL(0x0000080000000000)
#define SCTRCTL_CORSWAPINH _RISCV_ULL(0x0000100000000000)
#define SCTRCTL_RETINH _RISCV_ULL(0x0000200000000000)
#define SCTRCTL_INDLJMPINH _RISCV_ULL(0x0000400000000000)
#define SCTRCTL_DIRLJMPINH _RISCV_ULL(0x0000800000000000)
#define VSCTRCTL_U 0x0000000000000001
#define VSCTRCTL_S 0x0000000000000002
#define VSCTRCTL_RASEMU 0x0000000000000080
#define VSCTRCTL_STE 0x0000000000000100
#define VSCTRCTL_BPFRZ 0x0000000000000800
#define VSCTRCTL_LCOFIFRZ 0x0000000000001000
#define VSCTRCTL_EXCINH 0x0000000200000000
#define VSCTRCTL_INTRINH 0x0000000400000000
#define VSCTRCTL_TRETINH 0x0000000800000000
#define VSCTRCTL_NTBREN 0x0000001000000000
#define VSCTRCTL_TKBRINH 0x0000002000000000
#define VSCTRCTL_INDCALLINH 0x0000010000000000
#define VSCTRCTL_DIRCALLINH 0x0000020000000000
#define VSCTRCTL_INDJMPINH 0x0000040000000000
#define VSCTRCTL_DIRJMPINH 0x0000080000000000
#define VSCTRCTL_CORSWAPINH 0x0000100000000000
#define VSCTRCTL_RETINH 0x0000200000000000
#define VSCTRCTL_INDLJMPINH 0x0000400000000000
#define VSCTRCTL_DIRLJMPINH 0x0000800000000000
#define VSCTRCTL_CUSTOM 0xF000000000000000
#define VSCTRCTL_U _RISCV_ULL(0x0000000000000001)
#define VSCTRCTL_S _RISCV_ULL(0x0000000000000002)
#define VSCTRCTL_RASEMU _RISCV_ULL(0x0000000000000080)
#define VSCTRCTL_STE _RISCV_ULL(0x0000000000000100)
#define VSCTRCTL_BPFRZ _RISCV_ULL(0x0000000000000800)
#define VSCTRCTL_LCOFIFRZ _RISCV_ULL(0x0000000000001000)
#define VSCTRCTL_EXCINH _RISCV_ULL(0x0000000200000000)
#define VSCTRCTL_INTRINH _RISCV_ULL(0x0000000400000000)
#define VSCTRCTL_TRETINH _RISCV_ULL(0x0000000800000000)
#define VSCTRCTL_NTBREN _RISCV_ULL(0x0000001000000000)
#define VSCTRCTL_TKBRINH _RISCV_ULL(0x0000002000000000)
#define VSCTRCTL_INDCALLINH _RISCV_ULL(0x0000010000000000)
#define VSCTRCTL_DIRCALLINH _RISCV_ULL(0x0000020000000000)
#define VSCTRCTL_INDJMPINH _RISCV_ULL(0x0000040000000000)
#define VSCTRCTL_DIRJMPINH _RISCV_ULL(0x0000080000000000)
#define VSCTRCTL_CORSWAPINH _RISCV_ULL(0x0000100000000000)
#define VSCTRCTL_RETINH _RISCV_ULL(0x0000200000000000)
#define VSCTRCTL_INDLJMPINH _RISCV_ULL(0x0000400000000000)
#define VSCTRCTL_DIRLJMPINH _RISCV_ULL(0x0000800000000000)
#define VSCTRCTL_CUSTOM _RISCV_ULL(0xF000000000000000)
#define SCTRDEPTH_DEPTH 0x00000007
#define SCTRDEPTH_DEPTH _RISCV_UL(0x00000007)
#define SCTRSTATUS_WRPTR 0x000000FF
#define SCTRSTATUS_FROZEN 0x80000000
#define SCTRSTATUS_WRPTR _RISCV_UL(0x000000FF)
#define SCTRSTATUS_FROZEN _RISCV_UL(0x80000000)
#define SCTR_ENTRY_BASE 0x200
#define SCTR_ENTRY_BASE _RISCV_UL(0x200)
#define SCTR_SOURCE_V 0x0000000000000001
#define SCTR_SOURCE_PC 0xFFFFFFFFFFFFFFFE
#define SCTR_SOURCE_V _RISCV_ULL(0x0000000000000001)
#define SCTR_SOURCE_PC _RISCV_ULL(0xFFFFFFFFFFFFFFFE)
#define SCTR_TARGET_MISP 0x0000000000000001
#define SCTR_TARGET_PC 0xFFFFFFFFFFFFFFFE
#define SCTR_TARGET_MISP _RISCV_ULL(0x0000000000000001)
#define SCTR_TARGET_PC _RISCV_ULL(0xFFFFFFFFFFFFFFFE)
#define SCTR_DATA_TYPE 0x000000000000000F
#define SCTR_DATA_CCV 0x0000000000008000
#define SCTR_DATA_CC 0x00000000FFFF0000
#define SCTR_DATA_TYPE _RISCV_ULL(0x000000000000000F)
#define SCTR_DATA_CCV _RISCV_ULL(0x0000000000008000)
#define SCTR_DATA_CC _RISCV_ULL(0x00000000FFFF0000)
#define IRQ_U_SOFT 0
#define IRQ_S_SOFT 1
@ -495,19 +503,19 @@
#define PTE_A 0x040 /* Accessed */
#define PTE_D 0x080 /* Dirty */
#define PTE_SOFT 0x300 /* Reserved for Software */
#define PTE_SVRSW60T59B 0x1800000000000000 /* Svrsw60t59b: Reserved for software use */
#define PTE_RSVD 0x07C0000000000000 /* Reserved for future standard use */
#define PTE_PBMT 0x6000000000000000 /* Svpbmt: Page-based memory types */
#define PTE_N 0x8000000000000000 /* Svnapot: NAPOT translation contiguity */
#define PTE_ATTR 0xFFC0000000000000 /* All attributes and reserved bits */
#define PTE_SVRSW60T59B _RISCV_ULL(0x1800000000000000) /* Svrsw60t59b: Reserved for software use */
#define PTE_RSVD _RISCV_ULL(0x07C0000000000000) /* Reserved for future standard use */
#define PTE_PBMT _RISCV_ULL(0x6000000000000000) /* Svpbmt: Page-based memory types */
#define PTE_N _RISCV_ULL(0x8000000000000000) /* Svnapot: NAPOT translation contiguity */
#define PTE_ATTR _RISCV_ULL(0xFFC0000000000000) /* All attributes and reserved bits */
#define PTE_PPN_SHIFT 10
#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
/* srmcfg CSR fields */
#define SRMCFG_RCID 0x00000FFF
#define SRMCFG_MCID 0x0FFF0000
#define SRMCFG_RCID _RISCV_UL(0x00000FFF)
#define SRMCFG_MCID _RISCV_UL(0x0FFF0000)
/* software check exception xtval codes */
#define LANDING_PAD_FAULT 2
@ -717,6 +725,8 @@
#define MASK_BNE 0x707f
#define MATCH_BNEI 0x3063
#define MASK_BNEI 0x707f
#define MATCH_BREV8 0x68705013
#define MASK_BREV8 0xfff0707f
#define MATCH_BSET 0x28001033
#define MASK_BSET 0xfe00707f
#define MATCH_BSETI 0x28001013
@ -1255,10 +1265,6 @@
#define MASK_FSUB_S 0xfe00007f
#define MATCH_FSW 0x2027
#define MASK_FSW 0x707f
#define MATCH_GORCI 0x28005013
#define MASK_GORCI 0xfc00707f
#define MATCH_GREVI 0x68005013
#define MASK_GREVI 0xfc00707f
#define MATCH_HFENCE_GVMA 0x62000073
#define MASK_HFENCE_GVMA 0xfe007fff
#define MATCH_HFENCE_VVMA 0x22000073
@ -1435,6 +1441,8 @@
#define MASK_MULW 0xfe00707f
#define MATCH_OR 0x6033
#define MASK_OR 0xfe00707f
#define MATCH_ORC_B 0x28705013
#define MASK_ORC_B 0xfff0707f
#define MATCH_ORI 0x6013
#define MASK_ORI 0x707f
#define MATCH_ORN 0x40006033
@ -1461,6 +1469,10 @@
#define MASK_REMUW 0xfe00707f
#define MATCH_REMW 0x200603b
#define MASK_REMW 0xfe00707f
#define MATCH_REV8 0x6b805013
#define MASK_REV8 0xfff0707f
#define MATCH_REV8_RV32 0x69805013
#define MASK_REV8_RV32 0xfff0707f
#define MATCH_ROL 0x60001033
#define MASK_ROL 0xfe00707f
#define MATCH_ROLW 0x6000103b
@ -1541,8 +1553,6 @@
#define MASK_SHA512SUM1 0xfff0707f
#define MATCH_SHA512SUM1R 0x52000033
#define MASK_SHA512SUM1R 0xfe00707f
#define MATCH_SHFLI 0x8001013
#define MASK_SHFLI 0xfe00707f
#define MATCH_SINVAL_VMA 0x16000073
#define MASK_SINVAL_VMA 0xfe007fff
#define MATCH_SLL 0x1033
@ -1617,8 +1627,8 @@
#define MASK_SW 0x707f
#define MATCH_SW_RL 0x3a00202f
#define MASK_SW_RL 0xfa007fff
#define MATCH_UNSHFLI 0x8005013
#define MASK_UNSHFLI 0xfe00707f
#define MATCH_UNZIP 0x8f05013
#define MASK_UNZIP 0xfff0707f
#define MATCH_VAADD_VV 0x24002057
#define MASK_VAADD_VV 0xfc00707f
#define MATCH_VAADD_VX 0x24006057
@ -1627,6 +1637,12 @@
#define MASK_VAADDU_VV 0xfc00707f
#define MATCH_VAADDU_VX 0x20006057
#define MASK_VAADDU_VX 0xfc00707f
#define MATCH_VABD_VV 0x44002057
#define MASK_VABD_VV 0xfc00707f
#define MATCH_VABDU_VV 0x4c002057
#define MASK_VABDU_VV 0xfc00707f
#define MATCH_VABS_V 0x48082057
#define MASK_VABS_V 0xfc0ff07f
#define MATCH_VADC_VIM 0x40003057
#define MASK_VADC_VIM 0xfe00707f
#define MATCH_VADC_VVM 0x40000057
@ -2209,6 +2225,10 @@
#define MASK_VOR_VV 0xfc00707f
#define MATCH_VOR_VX 0x28004057
#define MASK_VOR_VX 0xfc00707f
#define MATCH_VPAIRE_VV 0x3c000057
#define MASK_VPAIRE_VV 0xfc00707f
#define MATCH_VPAIRO_VV 0x3c002057
#define MASK_VPAIRO_VV 0xfc00707f
#define MATCH_VQBDOTS_VV 0xbc000077
#define MASK_VQBDOTS_VV 0xfc00707f
#define MATCH_VQBDOTU_VV 0xb8000077
@ -2423,6 +2443,14 @@
#define MASK_VSUXEI64_V 0x1c00707f
#define MATCH_VSUXEI8_V 0x4000027
#define MASK_VSUXEI8_V 0x1c00707f
#define MATCH_VUNZIPE_V 0x4805a057
#define MASK_VUNZIPE_V 0xfc0ff07f
#define MATCH_VUNZIPO_V 0x4807a057
#define MASK_VUNZIPO_V 0xfc0ff07f
#define MATCH_VWABDA_VV 0x54002057
#define MASK_VWABDA_VV 0xfc00707f
#define MATCH_VWABDAU_VV 0x58002057
#define MASK_VWABDAU_VV 0xfc00707f
#define MATCH_VWADD_VV 0xc4002057
#define MASK_VWADD_VV 0xfc00707f
#define MATCH_VWADD_VX 0xc4006057
@ -2503,6 +2531,8 @@
#define MASK_VZEXT_VF4 0xfc0ff07f
#define MATCH_VZEXT_VF8 0x48012057
#define MASK_VZEXT_VF8 0xfc0ff07f
#define MATCH_VZIP_VV 0xf8002057
#define MASK_VZIP_VV 0xfc00707f
#define MATCH_WFI 0x10500073
#define MASK_WFI 0xffffffff
#define MATCH_WRS_NTO 0xd00073
@ -2523,6 +2553,8 @@
#define MASK_XPERM4 0xfe00707f
#define MATCH_XPERM8 0x28004033
#define MASK_XPERM8 0xfe00707f
#define MATCH_ZIP 0x8f01013
#define MASK_ZIP 0xfff0707f
#define CSR_FFLAGS 0x1
#define CSR_FRM 0x2
@ -3192,6 +3224,7 @@ DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
DECLARE_INSN(bnei, MATCH_BNEI, MASK_BNEI)
DECLARE_INSN(brev8, MATCH_BREV8, MASK_BREV8)
DECLARE_INSN(bset, MATCH_BSET, MASK_BSET)
DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
@ -3461,8 +3494,6 @@ DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H)
DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q)
DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI)
DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI)
DECLARE_INSN(hfence_gvma, MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA)
DECLARE_INSN(hfence_vvma, MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA)
DECLARE_INSN(hinval_gvma, MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA)
@ -3551,6 +3582,7 @@ DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
DECLARE_INSN(or, MATCH_OR, MASK_OR)
DECLARE_INSN(orc_b, MATCH_ORC_B, MASK_ORC_B)
DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
DECLARE_INSN(orn, MATCH_ORN, MASK_ORN)
DECLARE_INSN(pack, MATCH_PACK, MASK_PACK)
@ -3564,6 +3596,8 @@ DECLARE_INSN(rem, MATCH_REM, MASK_REM)
DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
DECLARE_INSN(rev8, MATCH_REV8, MASK_REV8)
DECLARE_INSN(rev8_rv32, MATCH_REV8_RV32, MASK_REV8_RV32)
DECLARE_INSN(rol, MATCH_ROL, MASK_ROL)
DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW)
DECLARE_INSN(ror, MATCH_ROR, MASK_ROR)
@ -3604,7 +3638,6 @@ DECLARE_INSN(sha512sum0, MATCH_SHA512SUM0, MASK_SHA512SUM0)
DECLARE_INSN(sha512sum0r, MATCH_SHA512SUM0R, MASK_SHA512SUM0R)
DECLARE_INSN(sha512sum1, MATCH_SHA512SUM1, MASK_SHA512SUM1)
DECLARE_INSN(sha512sum1r, MATCH_SHA512SUM1R, MASK_SHA512SUM1R)
DECLARE_INSN(shfli, MATCH_SHFLI, MASK_SHFLI)
DECLARE_INSN(sinval_vma, MATCH_SINVAL_VMA, MASK_SINVAL_VMA)
DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
@ -3642,11 +3675,14 @@ DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
DECLARE_INSN(sw, MATCH_SW, MASK_SW)
DECLARE_INSN(sw_rl, MATCH_SW_RL, MASK_SW_RL)
DECLARE_INSN(unshfli, MATCH_UNSHFLI, MASK_UNSHFLI)
DECLARE_INSN(unzip, MATCH_UNZIP, MASK_UNZIP)
DECLARE_INSN(vaadd_vv, MATCH_VAADD_VV, MASK_VAADD_VV)
DECLARE_INSN(vaadd_vx, MATCH_VAADD_VX, MASK_VAADD_VX)
DECLARE_INSN(vaaddu_vv, MATCH_VAADDU_VV, MASK_VAADDU_VV)
DECLARE_INSN(vaaddu_vx, MATCH_VAADDU_VX, MASK_VAADDU_VX)
DECLARE_INSN(vabd_vv, MATCH_VABD_VV, MASK_VABD_VV)
DECLARE_INSN(vabdu_vv, MATCH_VABDU_VV, MASK_VABDU_VV)
DECLARE_INSN(vabs_v, MATCH_VABS_V, MASK_VABS_V)
DECLARE_INSN(vadc_vim, MATCH_VADC_VIM, MASK_VADC_VIM)
DECLARE_INSN(vadc_vvm, MATCH_VADC_VVM, MASK_VADC_VVM)
DECLARE_INSN(vadc_vxm, MATCH_VADC_VXM, MASK_VADC_VXM)
@ -3938,6 +3974,8 @@ DECLARE_INSN(vnsrl_wx, MATCH_VNSRL_WX, MASK_VNSRL_WX)
DECLARE_INSN(vor_vi, MATCH_VOR_VI, MASK_VOR_VI)
DECLARE_INSN(vor_vv, MATCH_VOR_VV, MASK_VOR_VV)
DECLARE_INSN(vor_vx, MATCH_VOR_VX, MASK_VOR_VX)
DECLARE_INSN(vpaire_vv, MATCH_VPAIRE_VV, MASK_VPAIRE_VV)
DECLARE_INSN(vpairo_vv, MATCH_VPAIRO_VV, MASK_VPAIRO_VV)
DECLARE_INSN(vqbdots_vv, MATCH_VQBDOTS_VV, MASK_VQBDOTS_VV)
DECLARE_INSN(vqbdotu_vv, MATCH_VQBDOTU_VV, MASK_VQBDOTU_VV)
DECLARE_INSN(vqdot_vv, MATCH_VQDOT_VV, MASK_VQDOT_VV)
@ -4045,6 +4083,10 @@ DECLARE_INSN(vsuxei16_v, MATCH_VSUXEI16_V, MASK_VSUXEI16_V)
DECLARE_INSN(vsuxei32_v, MATCH_VSUXEI32_V, MASK_VSUXEI32_V)
DECLARE_INSN(vsuxei64_v, MATCH_VSUXEI64_V, MASK_VSUXEI64_V)
DECLARE_INSN(vsuxei8_v, MATCH_VSUXEI8_V, MASK_VSUXEI8_V)
DECLARE_INSN(vunzipe_v, MATCH_VUNZIPE_V, MASK_VUNZIPE_V)
DECLARE_INSN(vunzipo_v, MATCH_VUNZIPO_V, MASK_VUNZIPO_V)
DECLARE_INSN(vwabda_vv, MATCH_VWABDA_VV, MASK_VWABDA_VV)
DECLARE_INSN(vwabdau_vv, MATCH_VWABDAU_VV, MASK_VWABDAU_VV)
DECLARE_INSN(vwadd_vv, MATCH_VWADD_VV, MASK_VWADD_VV)
DECLARE_INSN(vwadd_vx, MATCH_VWADD_VX, MASK_VWADD_VX)
DECLARE_INSN(vwadd_wv, MATCH_VWADD_WV, MASK_VWADD_WV)
@ -4085,6 +4127,7 @@ DECLARE_INSN(vxor_vx, MATCH_VXOR_VX, MASK_VXOR_VX)
DECLARE_INSN(vzext_vf2, MATCH_VZEXT_VF2, MASK_VZEXT_VF2)
DECLARE_INSN(vzext_vf4, MATCH_VZEXT_VF4, MASK_VZEXT_VF4)
DECLARE_INSN(vzext_vf8, MATCH_VZEXT_VF8, MASK_VZEXT_VF8)
DECLARE_INSN(vzip_vv, MATCH_VZIP_VV, MASK_VZIP_VV)
DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO)
DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO)
@ -4095,6 +4138,7 @@ DECLARE_INSN(xperm16, MATCH_XPERM16, MASK_XPERM16)
DECLARE_INSN(xperm32, MATCH_XPERM32, MASK_XPERM32)
DECLARE_INSN(xperm4, MATCH_XPERM4, MASK_XPERM4)
DECLARE_INSN(xperm8, MATCH_XPERM8, MASK_XPERM8)
DECLARE_INSN(zip, MATCH_ZIP, MASK_ZIP)
#endif
#ifdef DECLARE_CSR
DECLARE_CSR(fflags, CSR_FFLAGS)

3
riscv/insns/brev8.h
View File

@ -0,0 +1,3 @@
require_extension(EXT_ZBKB);
#include "grevi.h"

2
riscv/insns/gorci.h
View File

@ -1,5 +1,3 @@
// Zbb contains orc.b but not general gorci
require(((SHAMT == 7) && p->extension_enabled(EXT_ZBB)));
require(SHAMT < xlen);
reg_t x = RS1;
if (SHAMT & 1) x |= ((x & 0x5555555555555555LL) << 1) | ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);

4
riscv/insns/grevi.h
View File

@ -1,7 +1,3 @@
// Zbb contains rev8 but not general grevi
// Zbkb contains rev8 and brev8 (a.k.a. rev.b) but not general grevi
require(((SHAMT == xlen - 8) && (p->extension_enabled(EXT_ZBB) || p->extension_enabled(EXT_ZBKB))) //rev8
|| ((SHAMT == 7) && p->extension_enabled(EXT_ZBKB))); // rev8.b
require(SHAMT < xlen);
reg_t x = RS1;
if (SHAMT & 1) x = ((x & 0x5555555555555555LL) << 1) | ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);

3
riscv/insns/orc_b.h
View File

@ -0,0 +1,3 @@
require_extension(EXT_ZBB);
#include "gorci.h"

4
riscv/insns/rev8.h
View File

@ -0,0 +1,4 @@
require_rv64;
require_either_extension(EXT_ZBB, EXT_ZBKB);
#include "grevi.h"

4
riscv/insns/rev8_rv32.h
View File

@ -0,0 +1,4 @@
require_rv32;
require_either_extension(EXT_ZBB, EXT_ZBKB);
#include "grevi.h"

2
riscv/insns/shfli.h
View File

@ -1,6 +1,4 @@
// Zbkb contains zip but not general shfli
require_rv32;
require(((insn.rs2() == (xlen / 2 - 1)) && p->extension_enabled(EXT_ZBKB)));
require(SHAMT < (xlen/2));
reg_t x = RS1;
if (SHAMT & 16) x = (x & 0xFFFF00000000FFFFLL) | ((x & 0x0000FFFF00000000LL) >> 16) | ((x & 0x00000000FFFF0000LL) << 16);

2
riscv/insns/unshfli.h
View File

@ -1,6 +1,4 @@
// Zbkb contains unzip but not general unshfli
require_rv32;
require(((insn.rs2() == (xlen / 2 - 1)) && p->extension_enabled(EXT_ZBKB)));
require(SHAMT < (xlen/2));
reg_t x = RS1;
if (SHAMT & 1) x = (x & 0x9999999999999999LL) | ((x & 0x4444444444444444LL) >> 1) | ((x & 0x2222222222222222LL) << 1);

3
riscv/insns/unzip.h
View File

@ -0,0 +1,3 @@
require_extension(EXT_ZBKB);
#include "unshfli.h"

3
riscv/insns/zip.h
View File

@ -0,0 +1,3 @@
require_extension(EXT_ZBKB);
#include "shfli.h"

10
riscv/riscv.mk.in
View File

@ -413,8 +413,10 @@ riscv_insn_ext_b = \
clzw \
ctz \
ctzw \
gorci \
grevi \
orc_b \
rev8 \
rev8_rv32 \
brev8 \
max \
maxu \
min \
@ -441,9 +443,9 @@ riscv_insn_ext_b = \
bseti \
sext_b \
sext_h \
shfli \
zip \
slli_uw \
unshfli \
unzip \
xnor \
xperm4 \
xperm8 \

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