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Clear EVEC LSBs, which kindly prevents a segfault

mvp
Andrew Waterman 12 years ago
parent
commit
e50ddde0ff
  1. 2
      riscv/processor.cc

2
riscv/processor.cc

@ -244,7 +244,7 @@ reg_t processor_t::set_pcr(int which, reg_t val)
state.epc = val;
break;
case CSR_EVEC:
state.evec = val;
state.evec = val & ~3;
break;
case CSR_CYCLE:
case CSR_TIME:

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