add hwacha vfmsv instructions

hwacha/encodings_hwacha.h

@@ -73,8 +73,9 @@
 #define MASK_VFLSEGSTD  0x1e00707f
 #define MASK_VFLSEGSTW  0x1e00707f
 #define MASK_VFLSEGW  0x1ff0707f
-#define MASK_VFMSV  0xfff0707f
 #define MASK_VFMVV  0xfff0707f
+#define MASK_VFMSV_S  0xfff0707f
+#define MASK_VFMSV_D  0xfff0707f
 #define MASK_VFSSEGD  0x1ff0707f
 #define MASK_VFSSEGSTD  0x1e00707f
 #define MASK_VFSSEGSTW  0x1e00707f
@@ -120,8 +121,9 @@
 #define MATCH_VFLSEGSTD 0x1600305b
 #define MATCH_VFLSEGSTW 0x1400305b
 #define MATCH_VFLSEGW 0x1400205b
-#define MATCH_VFMSV 0x1200202b
+#define MATCH_VFMVV 0x1000002b
-#define MATCH_VFMVV 0x1200002b
+#define MATCH_VFMSV_S 0x1000202b
+#define MATCH_VFMSV_D 0x1200202b
 #define MATCH_VFSSEGD 0x1600207b
 #define MATCH_VFSSEGSTD 0x1600307b
 #define MATCH_VFSSEGSTW 0x1400307b

hwacha/hwacha_disasm.cc

@@ -133,7 +133,8 @@ std::vector<disasm_insn_t*> hwacha_t::get_disasms()
   DISASM_INSN("vmvv", vmvv, 0, {&vxrd, &vxrs1});
   DISASM_INSN("vmsv", vmsv, 0, {&vxrd, &xrs1});
   DISASM_INSN("vfmvv", vfmvv, 0, {&vfrd, &vfrs1});
-  DISASM_INSN("vfmsv", vfmsv, 0, {&vfrd, &xrs1});
+  DISASM_INSN("vfmsv.s", vfmsv_s, 0, {&vfrd, &xrs1});
+  DISASM_INSN("vfmsv.d", vfmsv_d, 0, {&vfrd, &xrs1});
   DISASM_INSN("vf", vf, 0, {&vf_addr});
 
   DISASM_INSN("vxcptcause", vxcptcause, 0, {&xrd});

hwacha/insns/vfmsv_s.h

@@ -0,0 +1,3 @@
+for (uint32_t i=0; i<VL; i++) {
+  UT_WRITE_FRD(i, XS1);
+}

hwacha/opcodes_hwacha.h

@@ -5,7 +5,8 @@ DECLARE_INSN(vflsegd, MATCH_VFLSEGD, MASK_VFLSEGD)
 DECLARE_INSN(vflsegstd, MATCH_VFLSEGSTD, MASK_VFLSEGSTD)
 DECLARE_INSN(vflsegstw, MATCH_VFLSEGSTW, MASK_VFLSEGSTW)
 DECLARE_INSN(vflsegw, MATCH_VFLSEGW, MASK_VFLSEGW)
-DECLARE_INSN(vfmsv, MATCH_VFMSV, MASK_VFMSV)
+DECLARE_INSN(vfmsv_d, MATCH_VFMSV_D, MASK_VFMSV_D)
+DECLARE_INSN(vfmsv_s, MATCH_VFMSV_S, MASK_VFMSV_S)
 DECLARE_INSN(vfmvv, MATCH_VFMVV, MASK_VFMVV)
 DECLARE_INSN(vfssegd, MATCH_VFSSEGD, MASK_VFSSEGD)
 DECLARE_INSN(vfssegstd, MATCH_VFSSEGSTD, MASK_VFSSEGSTD)