Add logged instruction variants to insn_desc_t

customext/cflush.cc

@@ -24,9 +24,9 @@ class cflush_t : public extension_t
 
   std::vector<insn_desc_t> get_instructions() {
     std::vector<insn_desc_t> insns;
-    insns.push_back((insn_desc_t){0xFC000073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush});
+    insns.push_back((insn_desc_t){0xFC000073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush});
-    insns.push_back((insn_desc_t){0xFC200073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush});
+    insns.push_back((insn_desc_t){0xFC200073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush});
-    insns.push_back((insn_desc_t){0xFC100073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush});
+    insns.push_back((insn_desc_t){0xFC100073, 0xFFF07FFF, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush, custom_cflush});
     return insns;
   }
 

riscv/processor.cc

@@ -999,12 +999,13 @@ insn_func_t processor_t::decode_insn(insn_t insn)
     opcode_cache[idx].match = insn.bits();
   }
 
-  return desc.func(xlen, rve);
+  return desc.func(xlen, rve, log_commits_enabled);
 }
 
 void processor_t::register_insn(insn_desc_t desc)
 {
-  assert(desc.rv32i && desc.rv64i && desc.rv32e && desc.rv64e);
+  assert(desc.fast_rv32i && desc.fast_rv64i && desc.fast_rv32e && desc.fast_rv64e &&
+         desc.logged_rv32i && desc.logged_rv64i && desc.logged_rv32e && desc.logged_rv64e);
 
   instructions.push_back(desc);
 }
@@ -1058,6 +1059,10 @@ void processor_t::register_base_instructions()
     extern reg_t fast_rv64i_##name(processor_t*, insn_t, reg_t); \
     extern reg_t fast_rv32e_##name(processor_t*, insn_t, reg_t); \
     extern reg_t fast_rv64e_##name(processor_t*, insn_t, reg_t); \
+    extern reg_t logged_rv32i_##name(processor_t*, insn_t, reg_t); \
+    extern reg_t logged_rv64i_##name(processor_t*, insn_t, reg_t); \
+    extern reg_t logged_rv32e_##name(processor_t*, insn_t, reg_t); \
+    extern reg_t logged_rv64e_##name(processor_t*, insn_t, reg_t); \
     if (name##_supported) { \
       register_insn((insn_desc_t) { \
         name##_match, \
@@ -1065,7 +1070,11 @@ void processor_t::register_base_instructions()
         fast_rv32i_##name, \
         fast_rv64i_##name, \
         fast_rv32e_##name, \
-        fast_rv64e_##name}); \
+        fast_rv64e_##name, \
+        logged_rv32i_##name, \
+        logged_rv64i_##name, \
+        logged_rv32e_##name, \
+        logged_rv64e_##name}); \
     }
   #include "insn_list.h"
   #undef DEFINE_INSN

riscv/processor.h

@@ -34,22 +34,34 @@ struct insn_desc_t
 {
   insn_bits_t match;
   insn_bits_t mask;
-  insn_func_t rv32i;
+  insn_func_t fast_rv32i;
-  insn_func_t rv64i;
+  insn_func_t fast_rv64i;
-  insn_func_t rv32e;
+  insn_func_t fast_rv32e;
-  insn_func_t rv64e;
+  insn_func_t fast_rv64e;
-
+  insn_func_t logged_rv32i;
-  insn_func_t func(int xlen, bool rve)
+  insn_func_t logged_rv64i;
+  insn_func_t logged_rv32e;
+  insn_func_t logged_rv64e;
+
+  insn_func_t func(int xlen, bool rve, bool logged)
   {
-    if (rve)
+    if (logged)
-      return xlen == 64 ? rv64e : rv32e;
+      if (rve)
+        return xlen == 64 ? logged_rv64e : logged_rv32e;
+      else
+        return xlen == 64 ? logged_rv64i : logged_rv32i;
     else
-      return xlen == 64 ? rv64i : rv32i;
+      if (rve)
+        return xlen == 64 ? fast_rv64e : fast_rv32e;
+      else
+        return xlen == 64 ? fast_rv64i : fast_rv32i;
   }
 
   static insn_desc_t illegal()
   {
-    return {0, 0, &illegal_instruction, &illegal_instruction, &illegal_instruction, &illegal_instruction};
+    return {0, 0,
+            &illegal_instruction, &illegal_instruction, &illegal_instruction, &illegal_instruction,
+            &illegal_instruction, &illegal_instruction, &illegal_instruction, &illegal_instruction};
   }
 };
 

riscv/rocc.cc

@@ -34,10 +34,18 @@ customX(3)
 std::vector<insn_desc_t> rocc_t::get_instructions()
 {
   std::vector<insn_desc_t> insns;
-  insns.push_back((insn_desc_t){0x0b, 0x7f, &::illegal_instruction, c0, &::illegal_instruction, c0});
+  insns.push_back((insn_desc_t){0x0b, 0x7f,
-  insns.push_back((insn_desc_t){0x2b, 0x7f, &::illegal_instruction, c1, &::illegal_instruction, c1});
+                                &::illegal_instruction, c0, &::illegal_instruction, c0,
-  insns.push_back((insn_desc_t){0x5b, 0x7f, &::illegal_instruction, c2, &::illegal_instruction, c2});
+                                &::illegal_instruction, c0, &::illegal_instruction, c0});
-  insns.push_back((insn_desc_t){0x7b, 0x7f, &::illegal_instruction, c3, &::illegal_instruction, c3});
+  insns.push_back((insn_desc_t){0x2b, 0x7f,
+                                &::illegal_instruction, c1, &::illegal_instruction, c1,
+                                &::illegal_instruction, c1, &::illegal_instruction, c1});
+  insns.push_back((insn_desc_t){0x5b, 0x7f,
+                                &::illegal_instruction, c2, &::illegal_instruction, c2,
+                                &::illegal_instruction, c2, &::illegal_instruction, c2});
+  insns.push_back((insn_desc_t){0x7b, 0x7f,
+                                &::illegal_instruction, c3, &::illegal_instruction, c3,
+                                &::illegal_instruction, c0, &::illegal_instruction, c3});
   return insns;
 }