ext: add zibi

It implement v0.6 version

reference
    https://github.com/riscv/zibi/releases/download/v0.6/zibi.pdf
    https://riscv.atlassian.net/wiki/spaces/USXX/pages/599261201/Branch+with+Immediate+Zibi+Ratification+Plan

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

disasm/disasm.cc

@@ -560,6 +560,12 @@ struct : public arg_t {
   }
 } p_imm6;
 
+struct : public arg_t {
+  std::string to_string(insn_t insn) const {
+    return std::to_string((int)insn.b_imm5());
+  }
+} b_imm5;
+
 struct : public arg_t {
   std::string to_string(insn_t insn) const {
     return std::to_string((int)insn.bs());
@@ -655,6 +661,11 @@ static void NOINLINE add_btype_insn(disassembler_t* d, const char* name, uint32_
   d->add_insn(new disasm_insn_t(name, match, mask, {&xrs1, &xrs2, &branch_target}));
 }
 
+static void NOINLINE add_bimmtype_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask)
+{
+  d->add_insn(new disasm_insn_t(name, match, mask, {&xrs1, &b_imm5, &branch_target}));
+}
+
 static void NOINLINE add_b1type_insn(disassembler_t* d, const char* name, uint32_t match, uint32_t mask)
 {
   const uint32_t mask_rs2 = 0x1fUL << 20;
@@ -833,6 +844,7 @@ void disassembler_t::add_instructions(const isa_parser_t* isa, bool strict)
   #define DEFINE_PREFETCH(code) DISASM_INSN(#code, code, 0, {&store_address})
   #define DEFINE_LTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &bigimm})
   #define DEFINE_BTYPE(code) add_btype_insn(this, #code, match_##code, mask_##code);
+  #define DEFINE_BIMMTYPE(code) add_bimmtype_insn(this, #code, match_##code, mask_##code);
   #define DEFINE_B1TYPE(name, code) add_b1type_insn(this, name, match_##code, mask_##code);
   #define DEFINE_XLOAD(code) add_xload_insn(this, #code, match_##code, mask_##code);
   #define DEFINE_XSTORE(code) add_xstore_insn(this, #code, match_##code, mask_##code);
@@ -1368,6 +1380,11 @@ void disassembler_t::add_instructions(const isa_parser_t* isa, bool strict)
     //DEFINE_R1TYPE(fcvt_q_h);
   }
 
+  if (ext_enabled(EXT_ZIBI)) {
+     DEFINE_BIMMTYPE(beqi)
+     DEFINE_BIMMTYPE(bnei)
+  }
+
   if (ext_enabled('Q')) {
     DEFINE_FLOAD(flq)
     DEFINE_FSTORE(fsq)

disasm/isa_parser.cc

@@ -205,6 +205,8 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv)
       extension_table[EXT_ZCMP] = true;
     } else if (ext_str == "zcmt") {
       extension_table[EXT_ZCMT] = true;
+    } else if (ext_str == "zibi") {
+      extension_table[EXT_ZIBI] = true;
     } else if (ext_str == "zk") {
       extension_table[EXT_ZBKB] = true;
       extension_table[EXT_ZBKC] = true;

riscv/decode.h

@@ -154,6 +154,8 @@ public:
   uint64_t p_imm5() { return x(20, 5); }
   uint64_t p_imm6() { return x(20, 6); }
 
+  uint64_t b_imm5() { return (x(20, 5) == 0) ? -1ul : x(20, 5); }
+
   uint64_t zcmp_regmask() {
     unsigned mask = 0;
     uint64_t rlist = rvc_rlist();

riscv/insns/beqi.h

@@ -0,0 +1,5 @@
+require_extension(EXT_ZIBI);
+
+if (RS1 == insn.b_imm5()) {
+  set_pc(BRANCH_TARGET);
+}

riscv/insns/bnei.h

@@ -0,0 +1,5 @@
+require_extension(EXT_ZIBI);
+
+if (RS1 != insn.b_imm5()) {
+  set_pc(BRANCH_TARGET);
+}

riscv/isa_parser.h

@@ -50,6 +50,7 @@ typedef enum {
   EXT_ZFINX,
   EXT_ZHINX,
   EXT_ZHINXMIN,
+  EXT_ZIBI,
   EXT_ZICCID,
   EXT_ZICBOM,
   EXT_ZICBOZ,

riscv/riscv.mk.in

@@ -1089,6 +1089,10 @@ riscv_insn_ext_zimop = \
 	mop_r_N \
 	mop_rr_N \
 
+riscv_insn_ext_zibi = \
+	beqi \
+	bnei \
+
 riscv_insn_ext_zcmop = \
 	c_mop_N \
 
@@ -1146,6 +1150,7 @@ riscv_insn_list = \
 	$(riscv_insn_priv) \
 	$(riscv_insn_smrnmi) \
 	$(riscv_insn_svinval) \
+	$(riscv_insn_ext_zibi) \
 	$(riscv_insn_ext_zimop) \
 	$(riscv_insn_ext_zcmop) \
 	$(riscv_insn_ext_zicfilp) \