From 6fd2bc98821ee58c83953403e8bb2666d99d1794 Mon Sep 17 00:00:00 2001 From: Chih-Min Chao Date: Wed, 4 Dec 2024 18:40:06 -0800 Subject: [PATCH] mmu: raise the prioity of misaligned superpage Based on the change in ttps://github.com/riscv/riscv-isa-manual/pull/1742 The priority of misaligned superpage is higer that Zicfiss cases Signed-off-by: Chih-Min Chao --- riscv/mmu.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 8b99c1d5..2301c8c4 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -553,6 +553,8 @@ reg_t mmu_t::walk(mem_access_info_t access_info) // not shadow stack access xwr=110 or xwr=010 page cause page fault // shadow stack access with PTE_X moved to following check break; + } else if ((ppn & ((reg_t(1) << ptshift) - 1)) != 0) { + break; } else if (ss_page && ((type == STORE && !ss_access) || access_info.flags.clean_inval)) { // non-shadow-stack store or CBO with xwr = 010 causes access-fault throw trap_store_access_fault(virt, addr, 0, 0); @@ -566,8 +568,6 @@ reg_t mmu_t::walk(mem_access_info_t access_info) type == LOAD ? !(sse && ss_page) && !(pte & PTE_R) && !(mxr && (pte & PTE_X)) : !(pte & PTE_W)) { break; - } else if ((ppn & ((reg_t(1) << ptshift) - 1)) != 0) { - break; } else { reg_t ad = PTE_A | ((type == STORE) * PTE_D);