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@ -32,14 +32,14 @@ |
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static inline reg_t read_xpr(hwacha_t* h, insn_t insn, uint32_t idx, size_t src) |
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{ |
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if (src >= h->get_ct_state()->nxpr) |
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h->take_exception(HWACHA_CAUSE_TVEC_ILLEGAL_REGID, insn.bits()); |
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h->take_exception(HWACHA_CAUSE_TVEC_ILLEGAL_REGID, uint32_t(insn.bits())); |
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return (h->get_ut_state(idx)->XPR[src]); |
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} |
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static inline void write_xpr(hwacha_t* h, insn_t insn, uint32_t idx, size_t dst, reg_t value) |
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{ |
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if (dst >= h->get_ct_state()->nxpr) |
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h->take_exception(HWACHA_CAUSE_TVEC_ILLEGAL_REGID, insn.bits()); |
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h->take_exception(HWACHA_CAUSE_TVEC_ILLEGAL_REGID, uint32_t(insn.bits())); |
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h->get_ut_state(idx)->XPR.write(dst, value); |
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} |
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@ -52,14 +52,14 @@ static inline void write_xpr(hwacha_t* h, insn_t insn, uint32_t idx, size_t dst, |
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static inline reg_t read_fpr(hwacha_t* h, insn_t insn, uint32_t idx, size_t src) |
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{ |
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if (src >= h->get_ct_state()->nfpr) |
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h->take_exception(HWACHA_CAUSE_TVEC_ILLEGAL_REGID, insn.bits()); |
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h->take_exception(HWACHA_CAUSE_TVEC_ILLEGAL_REGID, uint32_t(insn.bits())); |
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return (h->get_ut_state(idx)->FPR[src]); |
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} |
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static inline void write_fpr(hwacha_t* h, insn_t insn, uint32_t idx, size_t dst, reg_t value) |
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{ |
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if (dst >= h->get_ct_state()->nfpr) |
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h->take_exception(HWACHA_CAUSE_TVEC_ILLEGAL_REGID, insn.bits()); |
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h->take_exception(HWACHA_CAUSE_TVEC_ILLEGAL_REGID, uint32_t(insn.bits())); |
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h->get_ut_state(idx)->FPR.write(dst, value); |
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} |
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@ -100,6 +100,6 @@ static inline void write_fpr(hwacha_t* h, insn_t insn, uint32_t idx, size_t dst, |
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#define require_supervisor_hwacha \ |
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if (unlikely(!(p->get_state()->sr & SR_S))) \ |
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h->take_exception(HWACHA_CAUSE_PRIVILEGED_INSTRUCTION, insn.bits()); |
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h->take_exception(HWACHA_CAUSE_PRIVILEGED_INSTRUCTION, uint32_t(insn.bits())); |
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#endif |
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