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riscv-isa-sim
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Merge pull request #1299 from ptomsich/ptomsich/zfa 

Add Zfa support
pull/1263/head
Scott Johnson 3 years ago
committed by GitHub
parent
d70ea67df7 09140c07e1
commit
dc109aeb94
No known key found for this signature in database GPG Key ID: 4AEE18F83AFDEB23
38 changed files with 626 additions and 1 deletions
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  1. 1
      .gitignore
  2. 158
      riscv/encoding.h
  3. 58
      riscv/insns/fcvtmod_w_d.h
  4. 4
      riscv/insns/fleq_d.h
  5. 4
      riscv/insns/fleq_h.h
  6. 4
      riscv/insns/fleq_q.h
  7. 4
      riscv/insns/fleq_s.h
  8. 40
      riscv/insns/fli_d.h
  9. 40
      riscv/insns/fli_h.h
  10. 46
      riscv/insns/fli_q.h
  11. 40
      riscv/insns/fli_s.h
  12. 4
      riscv/insns/fltq_d.h
  13. 4
      riscv/insns/fltq_h.h
  14. 4
      riscv/insns/fltq_q.h
  15. 4
      riscv/insns/fltq_s.h
  16. 10
      riscv/insns/fmaxm_d.h
  17. 10
      riscv/insns/fmaxm_h.h
  18. 17
      riscv/insns/fmaxm_q.h
  19. 10
      riscv/insns/fmaxm_s.h
  20. 10
      riscv/insns/fminm_d.h
  21. 10
      riscv/insns/fminm_h.h
  22. 17
      riscv/insns/fminm_q.h
  23. 10
      riscv/insns/fminm_s.h
  24. 7
      riscv/insns/fmvh_x_d.h
  25. 7
      riscv/insns/fmvh_x_q.h
  26. 8
      riscv/insns/fmvp_d_x.h
  27. 8
      riscv/insns/fmvp_q_x.h
  28. 5
      riscv/insns/fround_d.h
  29. 5
      riscv/insns/fround_h.h
  30. 5
      riscv/insns/fround_q.h
  31. 5
      riscv/insns/fround_s.h
  32. 5
      riscv/insns/froundnx_d.h
  33. 5
      riscv/insns/froundnx_h.h
  34. 5
      riscv/insns/froundnx_q.h
  35. 5
      riscv/insns/froundnx_s.h
  36. 2
      riscv/isa_parser.cc
  37. 1
      riscv/isa_parser.h
  38. 45
      riscv/riscv.mk.in

1
.gitignore
View File

@ -6,3 +6,4 @@ autom4te.cache/
*.d
.gdb_history
.#*
*~

158
riscv/encoding.h
View File

@ -4,7 +4,7 @@
/*
* This file is auto-generated by running 'make' in
* https://github.com/riscv/riscv-opcodes (02b4866)
* https://github.com/riscv/riscv-opcodes (5adef50)
*/
#ifndef RISCV_CSR_ENCODING_H
@ -381,8 +381,12 @@
#define MASK_ADD8 0xfe00707f
#define MATCH_ADD_UW 0x800003b
#define MASK_ADD_UW 0xfe00707f
#define MATCH_ADDD 0x7b
#define MASK_ADDD 0xfe00707f
#define MATCH_ADDI 0x13
#define MASK_ADDI 0x707f
#define MATCH_ADDID 0x5b
#define MASK_ADDID 0x707f
#define MATCH_ADDIW 0x1b
#define MASK_ADDIW 0x707f
#define MATCH_ADDW 0x3b
@ -559,6 +563,10 @@
#define MASK_C_LHU 0xfc43
#define MATCH_C_LI 0x4001
#define MASK_C_LI 0xe003
#define MATCH_C_LQ 0x2000
#define MASK_C_LQ 0xe003
#define MATCH_C_LQSP 0x2002
#define MASK_C_LQSP 0xe003
#define MATCH_C_LUI 0x6001
#define MASK_C_LUI 0xe003
#define MATCH_C_LW 0x4000
@ -589,6 +597,10 @@
#define MASK_C_SH 0xfc43
#define MATCH_C_SLLI 0x2
#define MASK_C_SLLI 0xe003
#define MATCH_C_SQ 0xa000
#define MASK_C_SQ 0xe003
#define MATCH_C_SQSP 0xa002
#define MASK_C_SQSP 0xe003
#define MATCH_C_SRAI 0x8401
#define MASK_C_SRAI 0xec03
#define MATCH_C_SRLI 0x8001
@ -827,6 +839,8 @@
#define MASK_FCVT_WU_Q 0xfff0007f
#define MATCH_FCVT_WU_S 0xc0100053
#define MASK_FCVT_WU_S 0xfff0007f
#define MATCH_FCVTMOD_W_D 0xc2801053
#define MASK_FCVTMOD_W_D 0xfff0707f
#define MATCH_FDIV_D 0x1a000053
#define MASK_FDIV_D 0xfe00007f
#define MATCH_FDIV_H 0x1c000053
@ -857,8 +871,24 @@
#define MASK_FLE_Q 0xfe00707f
#define MATCH_FLE_S 0xa0000053
#define MASK_FLE_S 0xfe00707f
#define MATCH_FLEQ_D 0xa2004053
#define MASK_FLEQ_D 0xfe00707f
#define MATCH_FLEQ_H 0xa4004053
#define MASK_FLEQ_H 0xfe00707f
#define MATCH_FLEQ_Q 0xa6004053
#define MASK_FLEQ_Q 0xfe00707f
#define MATCH_FLEQ_S 0xa0004053
#define MASK_FLEQ_S 0xfe00707f
#define MATCH_FLH 0x1007
#define MASK_FLH 0x707f
#define MATCH_FLI_D 0xf2100053
#define MASK_FLI_D 0xfff0707f
#define MATCH_FLI_H 0xf4100053
#define MASK_FLI_H 0xfff0707f
#define MATCH_FLI_Q 0xf6100053
#define MASK_FLI_Q 0xfff0707f
#define MATCH_FLI_S 0xf0100053
#define MASK_FLI_S 0xfff0707f
#define MATCH_FLQ 0x4007
#define MASK_FLQ 0x707f
#define MATCH_FLT_D 0xa2001053
@ -869,6 +899,14 @@
#define MASK_FLT_Q 0xfe00707f
#define MATCH_FLT_S 0xa0001053
#define MASK_FLT_S 0xfe00707f
#define MATCH_FLTQ_D 0xa2005053
#define MASK_FLTQ_D 0xfe00707f
#define MATCH_FLTQ_H 0xa4005053
#define MASK_FLTQ_H 0xfe00707f
#define MATCH_FLTQ_Q 0xa6005053
#define MASK_FLTQ_Q 0xfe00707f
#define MATCH_FLTQ_S 0xa0005053
#define MASK_FLTQ_S 0xfe00707f
#define MATCH_FLW 0x2007
#define MASK_FLW 0x707f
#define MATCH_FMADD_D 0x2000043
@ -887,6 +925,14 @@
#define MASK_FMAX_Q 0xfe00707f
#define MATCH_FMAX_S 0x28001053
#define MASK_FMAX_S 0xfe00707f
#define MATCH_FMAXM_D 0x2a003053
#define MASK_FMAXM_D 0xfe00707f
#define MATCH_FMAXM_H 0x2c003053
#define MASK_FMAXM_H 0xfe00707f
#define MATCH_FMAXM_Q 0x2e003053
#define MASK_FMAXM_Q 0xfe00707f
#define MATCH_FMAXM_S 0x28003053
#define MASK_FMAXM_S 0xfe00707f
#define MATCH_FMIN_D 0x2a000053
#define MASK_FMIN_D 0xfe00707f
#define MATCH_FMIN_H 0x2c000053
@ -895,6 +941,14 @@
#define MASK_FMIN_Q 0xfe00707f
#define MATCH_FMIN_S 0x28000053
#define MASK_FMIN_S 0xfe00707f
#define MATCH_FMINM_D 0x2a002053
#define MASK_FMINM_D 0xfe00707f
#define MATCH_FMINM_H 0x2c002053
#define MASK_FMINM_H 0xfe00707f
#define MATCH_FMINM_Q 0x2e002053
#define MASK_FMINM_Q 0xfe00707f
#define MATCH_FMINM_S 0x28002053
#define MASK_FMINM_S 0xfe00707f
#define MATCH_FMSUB_D 0x2000047
#define MASK_FMSUB_D 0x600007f
#define MATCH_FMSUB_H 0x4000047
@ -923,6 +977,14 @@
#define MASK_FMV_X_H 0xfff0707f
#define MATCH_FMV_X_W 0xe0000053
#define MASK_FMV_X_W 0xfff0707f
#define MATCH_FMVH_X_D 0xe2100053
#define MASK_FMVH_X_D 0xfff0707f
#define MATCH_FMVH_X_Q 0xe6100053
#define MASK_FMVH_X_Q 0xfff0707f
#define MATCH_FMVP_D_X 0xb2100053
#define MASK_FMVP_D_X 0xfff0707f
#define MATCH_FMVP_Q_X 0xb6100053
#define MASK_FMVP_Q_X 0xfff0707f
#define MATCH_FNMADD_D 0x200004f
#define MASK_FNMADD_D 0x600007f
#define MATCH_FNMADD_H 0x400004f
@ -939,6 +1001,22 @@
#define MASK_FNMSUB_Q 0x600007f
#define MATCH_FNMSUB_S 0x4b
#define MASK_FNMSUB_S 0x600007f
#define MATCH_FROUND_D 0x42400053
#define MASK_FROUND_D 0xfff0007f
#define MATCH_FROUND_H 0x44400053
#define MASK_FROUND_H 0xfff0007f
#define MATCH_FROUND_Q 0x46400053
#define MASK_FROUND_Q 0xfff0007f
#define MATCH_FROUND_S 0x40400053
#define MASK_FROUND_S 0xfff0007f
#define MATCH_FROUNDNX_D 0x42500053
#define MASK_FROUNDNX_D 0xfff0007f
#define MATCH_FROUNDNX_H 0x44500053
#define MASK_FROUNDNX_H 0xfff0007f
#define MATCH_FROUNDNX_Q 0x46500053
#define MASK_FROUNDNX_Q 0xfff0007f
#define MATCH_FROUNDNX_S 0x40500053
#define MASK_FROUNDNX_S 0xfff0007f
#define MATCH_FSD 0x3027
#define MASK_FSD 0x707f
#define MATCH_FSGNJ_D 0x22000053
@ -1271,10 +1349,14 @@
#define MASK_LBU 0x707f
#define MATCH_LD 0x3003
#define MASK_LD 0x707f
#define MATCH_LDU 0x7003
#define MASK_LDU 0x707f
#define MATCH_LH 0x1003
#define MASK_LH 0x707f
#define MATCH_LHU 0x5003
#define MASK_LHU 0x707f
#define MATCH_LQ 0x300f
#define MASK_LQ 0x707f
#define MATCH_LR_D 0x1000302f
#define MASK_LR_D 0xf9f0707f
#define MATCH_LR_W 0x1000202f
@ -1501,6 +1583,8 @@
#define MASK_SLL32 0xfe00707f
#define MATCH_SLL8 0x5c000077
#define MASK_SLL8 0xfe00707f
#define MATCH_SLLD 0x107b
#define MASK_SLLD 0xfe00707f
#define MATCH_SLLI 0x1013
#define MASK_SLLI 0xfc00707f
#define MATCH_SLLI16 0x74000077
@ -1509,10 +1593,14 @@
#define MASK_SLLI32 0xfe00707f
#define MATCH_SLLI8 0x7c000077
#define MASK_SLLI8 0xff80707f
#define MATCH_SLLI_RV128 0x1013
#define MASK_SLLI_RV128 0xf800707f
#define MATCH_SLLI_RV32 0x1013
#define MASK_SLLI_RV32 0xfe00707f
#define MATCH_SLLI_UW 0x800101b
#define MASK_SLLI_UW 0xfc00707f
#define MATCH_SLLID 0x105b
#define MASK_SLLID 0xfc00707f
#define MATCH_SLLIW 0x101b
#define MASK_SLLIW 0xfe00707f
#define MATCH_SLLW 0x103b
@ -1625,6 +1713,8 @@
#define MASK_SMXDS 0xfe00707f
#define MATCH_SMXDS32 0x78002077
#define MASK_SMXDS32 0xfe00707f
#define MATCH_SQ 0x4023
#define MASK_SQ 0x707f
#define MATCH_SRA 0x40005033
#define MASK_SRA 0xfe00707f
#define MATCH_SRA16 0x50000077
@ -1641,6 +1731,8 @@
#define MASK_SRA8_U 0xfe00707f
#define MATCH_SRA_U 0x24001077
#define MASK_SRA_U 0xfe00707f
#define MATCH_SRAD 0x4000507b
#define MASK_SRAD 0xfe00707f
#define MATCH_SRAI 0x40005013
#define MASK_SRAI 0xfc00707f
#define MATCH_SRAI16 0x70000077
@ -1655,10 +1747,14 @@
#define MASK_SRAI8 0xff80707f
#define MATCH_SRAI8_U 0x78800077
#define MASK_SRAI8_U 0xff80707f
#define MATCH_SRAI_RV128 0x40005013
#define MASK_SRAI_RV128 0xf800707f
#define MATCH_SRAI_RV32 0x40005013
#define MASK_SRAI_RV32 0xfe00707f
#define MATCH_SRAI_U 0xd4001077
#define MASK_SRAI_U 0xfc00707f
#define MATCH_SRAID 0x4000505b
#define MASK_SRAID 0xfc00707f
#define MATCH_SRAIW 0x4000501b
#define MASK_SRAIW 0xfe00707f
#define MATCH_SRAIW_U 0x34001077
@ -1681,6 +1777,8 @@
#define MASK_SRL8 0xfe00707f
#define MATCH_SRL8_U 0x6a000077
#define MASK_SRL8_U 0xfe00707f
#define MATCH_SRLD 0x507b
#define MASK_SRLD 0xfe00707f
#define MATCH_SRLI 0x5013
#define MASK_SRLI 0xfc00707f
#define MATCH_SRLI16 0x72000077
@ -1695,8 +1793,12 @@
#define MASK_SRLI8 0xff80707f
#define MATCH_SRLI8_U 0x7a800077
#define MASK_SRLI8_U 0xff80707f
#define MATCH_SRLI_RV128 0x5013
#define MASK_SRLI_RV128 0xf800707f
#define MATCH_SRLI_RV32 0x5013
#define MASK_SRLI_RV32 0xfe00707f
#define MATCH_SRLID 0x505b
#define MASK_SRLID 0xfc00707f
#define MATCH_SRLIW 0x501b
#define MASK_SRLIW 0xfe00707f
#define MATCH_SRLW 0x503b
@ -1727,6 +1829,8 @@
#define MASK_SUB64 0xfe00707f
#define MATCH_SUB8 0x4a000077
#define MASK_SUB8 0xfe00707f
#define MATCH_SUBD 0x4000007b
#define MASK_SUBD 0xfe00707f
#define MATCH_SUBW 0x4000003b
#define MASK_SUBW 0xfe00707f
#define MATCH_SUNPKD810 0xac800077
@ -3347,7 +3451,9 @@ DECLARE_INSN(add32, MATCH_ADD32, MASK_ADD32)
DECLARE_INSN(add64, MATCH_ADD64, MASK_ADD64)
DECLARE_INSN(add8, MATCH_ADD8, MASK_ADD8)
DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW)
DECLARE_INSN(addd, MATCH_ADDD, MASK_ADDD)
DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
DECLARE_INSN(addid, MATCH_ADDID, MASK_ADDID)
DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
DECLARE_INSN(aes32dsi, MATCH_AES32DSI, MASK_AES32DSI)
@ -3436,6 +3542,8 @@ DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
DECLARE_INSN(c_lh, MATCH_C_LH, MASK_C_LH)
DECLARE_INSN(c_lhu, MATCH_C_LHU, MASK_C_LHU)
DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
DECLARE_INSN(c_lq, MATCH_C_LQ, MASK_C_LQ)
DECLARE_INSN(c_lqsp, MATCH_C_LQSP, MASK_C_LQSP)
DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
@ -3451,6 +3559,8 @@ DECLARE_INSN(c_sext_b, MATCH_C_SEXT_B, MASK_C_SEXT_B)
DECLARE_INSN(c_sext_h, MATCH_C_SEXT_H, MASK_C_SEXT_H)
DECLARE_INSN(c_sh, MATCH_C_SH, MASK_C_SH)
DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
DECLARE_INSN(c_sq, MATCH_C_SQ, MASK_C_SQ)
DECLARE_INSN(c_sqsp, MATCH_C_SQSP, MASK_C_SQSP)
DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
@ -3570,6 +3680,7 @@ DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
DECLARE_INSN(fcvt_wu_h, MATCH_FCVT_WU_H, MASK_FCVT_WU_H)
DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q)
DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
DECLARE_INSN(fcvtmod_w_d, MATCH_FCVTMOD_W_D, MASK_FCVTMOD_W_D)
DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
DECLARE_INSN(fdiv_h, MATCH_FDIV_H, MASK_FDIV_H)
DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q)
@ -3585,12 +3696,24 @@ DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
DECLARE_INSN(fle_h, MATCH_FLE_H, MASK_FLE_H)
DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q)
DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
DECLARE_INSN(fleq_d, MATCH_FLEQ_D, MASK_FLEQ_D)
DECLARE_INSN(fleq_h, MATCH_FLEQ_H, MASK_FLEQ_H)
DECLARE_INSN(fleq_q, MATCH_FLEQ_Q, MASK_FLEQ_Q)
DECLARE_INSN(fleq_s, MATCH_FLEQ_S, MASK_FLEQ_S)
DECLARE_INSN(flh, MATCH_FLH, MASK_FLH)
DECLARE_INSN(fli_d, MATCH_FLI_D, MASK_FLI_D)
DECLARE_INSN(fli_h, MATCH_FLI_H, MASK_FLI_H)
DECLARE_INSN(fli_q, MATCH_FLI_Q, MASK_FLI_Q)
DECLARE_INSN(fli_s, MATCH_FLI_S, MASK_FLI_S)
DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
DECLARE_INSN(flt_h, MATCH_FLT_H, MASK_FLT_H)
DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q)
DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
DECLARE_INSN(fltq_d, MATCH_FLTQ_D, MASK_FLTQ_D)
DECLARE_INSN(fltq_h, MATCH_FLTQ_H, MASK_FLTQ_H)
DECLARE_INSN(fltq_q, MATCH_FLTQ_Q, MASK_FLTQ_Q)
DECLARE_INSN(fltq_s, MATCH_FLTQ_S, MASK_FLTQ_S)
DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
DECLARE_INSN(fmadd_h, MATCH_FMADD_H, MASK_FMADD_H)
@ -3600,10 +3723,18 @@ DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
DECLARE_INSN(fmax_h, MATCH_FMAX_H, MASK_FMAX_H)
DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q)
DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
DECLARE_INSN(fmaxm_d, MATCH_FMAXM_D, MASK_FMAXM_D)
DECLARE_INSN(fmaxm_h, MATCH_FMAXM_H, MASK_FMAXM_H)
DECLARE_INSN(fmaxm_q, MATCH_FMAXM_Q, MASK_FMAXM_Q)
DECLARE_INSN(fmaxm_s, MATCH_FMAXM_S, MASK_FMAXM_S)
DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
DECLARE_INSN(fmin_h, MATCH_FMIN_H, MASK_FMIN_H)
DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q)
DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
DECLARE_INSN(fminm_d, MATCH_FMINM_D, MASK_FMINM_D)
DECLARE_INSN(fminm_h, MATCH_FMINM_H, MASK_FMINM_H)
DECLARE_INSN(fminm_q, MATCH_FMINM_Q, MASK_FMINM_Q)
DECLARE_INSN(fminm_s, MATCH_FMINM_S, MASK_FMINM_S)
DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
DECLARE_INSN(fmsub_h, MATCH_FMSUB_H, MASK_FMSUB_H)
DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q)
@ -3618,6 +3749,10 @@ DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X)
DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
DECLARE_INSN(fmv_x_h, MATCH_FMV_X_H, MASK_FMV_X_H)
DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W)
DECLARE_INSN(fmvh_x_d, MATCH_FMVH_X_D, MASK_FMVH_X_D)
DECLARE_INSN(fmvh_x_q, MATCH_FMVH_X_Q, MASK_FMVH_X_Q)
DECLARE_INSN(fmvp_d_x, MATCH_FMVP_D_X, MASK_FMVP_D_X)
DECLARE_INSN(fmvp_q_x, MATCH_FMVP_Q_X, MASK_FMVP_Q_X)
DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
DECLARE_INSN(fnmadd_h, MATCH_FNMADD_H, MASK_FNMADD_H)
DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q)
@ -3626,6 +3761,14 @@ DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
DECLARE_INSN(fnmsub_h, MATCH_FNMSUB_H, MASK_FNMSUB_H)
DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q)
DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
DECLARE_INSN(fround_d, MATCH_FROUND_D, MASK_FROUND_D)
DECLARE_INSN(fround_h, MATCH_FROUND_H, MASK_FROUND_H)
DECLARE_INSN(fround_q, MATCH_FROUND_Q, MASK_FROUND_Q)
DECLARE_INSN(fround_s, MATCH_FROUND_S, MASK_FROUND_S)
DECLARE_INSN(froundnx_d, MATCH_FROUNDNX_D, MASK_FROUNDNX_D)
DECLARE_INSN(froundnx_h, MATCH_FROUNDNX_H, MASK_FROUNDNX_H)
DECLARE_INSN(froundnx_q, MATCH_FROUNDNX_Q, MASK_FROUNDNX_Q)
DECLARE_INSN(froundnx_s, MATCH_FROUNDNX_S, MASK_FROUNDNX_S)
DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
DECLARE_INSN(fsgnj_h, MATCH_FSGNJ_H, MASK_FSGNJ_H)
@ -3792,8 +3935,10 @@ DECLARE_INSN(kwmmul_u, MATCH_KWMMUL_U, MASK_KWMMUL_U)
DECLARE_INSN(lb, MATCH_LB, MASK_LB)
DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
DECLARE_INSN(ld, MATCH_LD, MASK_LD)
DECLARE_INSN(ldu, MATCH_LDU, MASK_LDU)
DECLARE_INSN(lh, MATCH_LH, MASK_LH)
DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
DECLARE_INSN(lq, MATCH_LQ, MASK_LQ)
DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
@ -3907,12 +4052,15 @@ DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
DECLARE_INSN(sll16, MATCH_SLL16, MASK_SLL16)
DECLARE_INSN(sll32, MATCH_SLL32, MASK_SLL32)
DECLARE_INSN(sll8, MATCH_SLL8, MASK_SLL8)
DECLARE_INSN(slld, MATCH_SLLD, MASK_SLLD)
DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
DECLARE_INSN(slli16, MATCH_SLLI16, MASK_SLLI16)
DECLARE_INSN(slli32, MATCH_SLLI32, MASK_SLLI32)
DECLARE_INSN(slli8, MATCH_SLLI8, MASK_SLLI8)
DECLARE_INSN(slli_rv128, MATCH_SLLI_RV128, MASK_SLLI_RV128)
DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
DECLARE_INSN(sllid, MATCH_SLLID, MASK_SLLID)
DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
DECLARE_INSN(slo, MATCH_SLO, MASK_SLO)
@ -3969,6 +4117,7 @@ DECLARE_INSN(smulx16, MATCH_SMULX16, MASK_SMULX16)
DECLARE_INSN(smulx8, MATCH_SMULX8, MASK_SMULX8)
DECLARE_INSN(smxds, MATCH_SMXDS, MASK_SMXDS)
DECLARE_INSN(smxds32, MATCH_SMXDS32, MASK_SMXDS32)
DECLARE_INSN(sq, MATCH_SQ, MASK_SQ)
DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
DECLARE_INSN(sra16, MATCH_SRA16, MASK_SRA16)
DECLARE_INSN(sra16_u, MATCH_SRA16_U, MASK_SRA16_U)
@ -3977,6 +4126,7 @@ DECLARE_INSN(sra32_u, MATCH_SRA32_U, MASK_SRA32_U)
DECLARE_INSN(sra8, MATCH_SRA8, MASK_SRA8)
DECLARE_INSN(sra8_u, MATCH_SRA8_U, MASK_SRA8_U)
DECLARE_INSN(sra_u, MATCH_SRA_U, MASK_SRA_U)
DECLARE_INSN(srad, MATCH_SRAD, MASK_SRAD)
DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
DECLARE_INSN(srai16, MATCH_SRAI16, MASK_SRAI16)
DECLARE_INSN(srai16_u, MATCH_SRAI16_U, MASK_SRAI16_U)
@ -3984,8 +4134,10 @@ DECLARE_INSN(srai32, MATCH_SRAI32, MASK_SRAI32)
DECLARE_INSN(srai32_u, MATCH_SRAI32_U, MASK_SRAI32_U)
DECLARE_INSN(srai8, MATCH_SRAI8, MASK_SRAI8)
DECLARE_INSN(srai8_u, MATCH_SRAI8_U, MASK_SRAI8_U)
DECLARE_INSN(srai_rv128, MATCH_SRAI_RV128, MASK_SRAI_RV128)
DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32)
DECLARE_INSN(srai_u, MATCH_SRAI_U, MASK_SRAI_U)
DECLARE_INSN(sraid, MATCH_SRAID, MASK_SRAID)
DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
DECLARE_INSN(sraiw_u, MATCH_SRAIW_U, MASK_SRAIW_U)
DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
@ -3997,6 +4149,7 @@ DECLARE_INSN(srl32, MATCH_SRL32, MASK_SRL32)
DECLARE_INSN(srl32_u, MATCH_SRL32_U, MASK_SRL32_U)
DECLARE_INSN(srl8, MATCH_SRL8, MASK_SRL8)
DECLARE_INSN(srl8_u, MATCH_SRL8_U, MASK_SRL8_U)
DECLARE_INSN(srld, MATCH_SRLD, MASK_SRLD)
DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
DECLARE_INSN(srli16, MATCH_SRLI16, MASK_SRLI16)
DECLARE_INSN(srli16_u, MATCH_SRLI16_U, MASK_SRLI16_U)
@ -4004,7 +4157,9 @@ DECLARE_INSN(srli32, MATCH_SRLI32, MASK_SRLI32)
DECLARE_INSN(srli32_u, MATCH_SRLI32_U, MASK_SRLI32_U)
DECLARE_INSN(srli8, MATCH_SRLI8, MASK_SRLI8)
DECLARE_INSN(srli8_u, MATCH_SRLI8_U, MASK_SRLI8_U)
DECLARE_INSN(srli_rv128, MATCH_SRLI_RV128, MASK_SRLI_RV128)
DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
DECLARE_INSN(srlid, MATCH_SRLID, MASK_SRLID)
DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
DECLARE_INSN(sro, MATCH_SRO, MASK_SRO)
@ -4020,6 +4175,7 @@ DECLARE_INSN(sub16, MATCH_SUB16, MASK_SUB16)
DECLARE_INSN(sub32, MATCH_SUB32, MASK_SUB32)
DECLARE_INSN(sub64, MATCH_SUB64, MASK_SUB64)
DECLARE_INSN(sub8, MATCH_SUB8, MASK_SUB8)
DECLARE_INSN(subd, MATCH_SUBD, MASK_SUBD)
DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
DECLARE_INSN(sunpkd810, MATCH_SUNPKD810, MASK_SUNPKD810)
DECLARE_INSN(sunpkd820, MATCH_SUNPKD820, MASK_SUNPKD820)

58
riscv/insns/fcvtmod_w_d.h
View File

@ -0,0 +1,58 @@
require_extension('D');
require_extension(EXT_ZFA);
require_fp;
uint64_t a = FRS1_D.v;
uint32_t sign = signF64UI(a);
uint32_t exp = expF64UI(a);
uint64_t frac = fracF64UI(a);
bool inexact = false;
bool invalid = false;
if (exp == 0) {
inexact = (frac != 0);
frac = 0;
} else if (exp == 0x7ff) {
/* inf or NaN */
invalid = true;
frac = 0;
} else {
int true_exp = exp - 1023;
int shift = true_exp - 52;
/* Restore implicit bit. */
frac |= 1ull << 52;
/* Shift the fraction into place. */
if (shift >= 64) {
/* The fraction is shifted out entirely. */
frac = 0;
} else if ((shift >= 0) && (shift < 64)) {
/* The number is so large we must shift the fraction left. */
frac <<= shift;
} else if ((shift > -64) && (shift < 0)) {
/* Normal case -- shift right and notice if bits shift out. */
inexact = (frac << (64 + shift)) != 0;
frac >>= -shift;
} else {
/* The fraction is shifted out entirely. */
frac = 0;
}
/* Notice overflow or inexact exceptions. */
if (true_exp > 31 || frac > (sign ? 0x80000000ull : 0x7fffffff)) {
/* Overflow, for which this operation raises invalid. */
invalid = true;
}
/* Honor the sign. */
if (sign) {
frac = -frac;
}
}
WRITE_RD(sext32(frac));
STATE.fflags->write(STATE.fflags->read() |
(inexact ? softfloat_flag_inexact : 0) |
(invalid ? softfloat_flag_invalid : 0));

4
riscv/insns/fleq_d.h
View File

@ -0,0 +1,4 @@
require_extension('D');
require_extension(EXT_ZFA);
require_fp;
WRITE_RD(f64_le_quiet(FRS1_D, FRS2_D));

4
riscv/insns/fleq_h.h
View File

@ -0,0 +1,4 @@
require_extension(EXT_ZFH);
require_extension(EXT_ZFA);
require_fp;
WRITE_RD(f16_le_quiet(FRS1_H, FRS2_H));

4
riscv/insns/fleq_q.h
View File

@ -0,0 +1,4 @@
require_extension('Q');
require_extension(EXT_ZFA);
require_fp;
WRITE_RD(f128_le_quiet(f128(FRS1), f128(FRS2)));

4
riscv/insns/fleq_s.h
View File

@ -0,0 +1,4 @@
require_extension('F');
require_extension(EXT_ZFA);
require_fp;
WRITE_RD(f32_le_quiet(FRS1_F, FRS2_F));

40
riscv/insns/fli_d.h
View File

@ -0,0 +1,40 @@
require_extension('D');
require_extension(EXT_ZFA);
require_fp;
{
const uint64_t bits[32] = {
[0b00000] = 0xbff0000000000000ull, /* -1.0 */
[0b00001] = 0x0010000000000000ull, /* minimum positive normal */
[0b00010] = 0x3ef0000000000000ull, /* 1.0 * 2^-16 */
[0b00011] = 0x3f00000000000000ull, /* 1.0 * 2^-15 */
[0b00100] = 0x3f70000000000000ull, /* 1.0 * 2^-8 */
[0b00101] = 0x3f80000000000000ull, /* 1.0 * 2^-7 */
[0b00110] = 0x3fb0000000000000ull, /* 1.0 * 2^-4 */
[0b00111] = 0x3fc0000000000000ull, /* 1.0 * 2^-3 */
[0b01000] = 0x3fd0000000000000ull, /* 0.25 */
[0b01001] = 0x3fd4000000000000ull, /* 0.3125 */
[0b01010] = 0x3fd8000000000000ull, /* 0.375 */
[0b01011] = 0x3fdc000000000000ull, /* 0.4375 */
[0b01100] = 0x3fe0000000000000ull, /* 0.5 */
[0b01101] = 0x3fe4000000000000ull, /* 0.625 */
[0b01110] = 0x3fe8000000000000ull, /* 0.75 */
[0b01111] = 0x3fec000000000000ull, /* 0.875 */
[0b10000] = 0x3ff0000000000000ull, /* 1.0 */
[0b10001] = 0x3ff4000000000000ull, /* 1.25 */
[0b10010] = 0x3ff8000000000000ull, /* 1.5 */
[0b10011] = 0x3ffc000000000000ull, /* 1.75 */
[0b10100] = 0x4000000000000000ull, /* 2.0 */
[0b10101] = 0x4004000000000000ull, /* 2.5 */
[0b10110] = 0x4008000000000000ull, /* 3 */
[0b10111] = 0x4010000000000000ull, /* 4 */
[0b11000] = 0x4020000000000000ull, /* 8 */
[0b11001] = 0x4030000000000000ull, /* 16 */
[0b11010] = 0x4060000000000000ull, /* 2^7 */
[0b11011] = 0x4070000000000000ull, /* 2^8 */
[0b11100] = 0x40e0000000000000ull, /* 2^15 */
[0b11101] = 0x40f0000000000000ull, /* 2^16 */
[0b11110] = 0x7ff0000000000000ull, /* +inf */
[0b11111] = defaultNaNF64UI
};
WRITE_FRD_D(f64(bits[insn.rs1()]));
}

40
riscv/insns/fli_h.h
View File

@ -0,0 +1,40 @@
require_extension(EXT_ZFH);
require_extension(EXT_ZFA);
require_fp;
{
static const uint16_t bits[32] = {
[0b00000] = 0xbc00, /* -1.0 */
[0b00001] = 0x0400, /* minimum positive normal */
[0b00010] = 0x0100, /* 1.0 * 2^-16 */
[0b00011] = 0x0200, /* 1.0 * 2^-15 */
[0b00100] = 0x1c00, /* 1.0 * 2^-8 */
[0b00101] = 0x2000, /* 1.0 * 2^-7 */
[0b00110] = 0x2c00, /* 1.0 * 2^-4 */
[0b00111] = 0x3000, /* 1.0 * 2^-3 */
[0b01000] = 0x3400, /* 0.25 */
[0b01001] = 0x3500, /* 0.3125 */
[0b01010] = 0x3600, /* 0.375 */
[0b01011] = 0x3700, /* 0.4375 */
[0b01100] = 0x3800, /* 0.5 */
[0b01101] = 0x3900, /* 0.625 */
[0b01110] = 0x3a00, /* 0.75 */
[0b01111] = 0x3b00, /* 0.875 */
[0b10000] = 0x3c00, /* 1.0 */
[0b10001] = 0x3d00, /* 1.25 */
[0b10010] = 0x3e00, /* 1.5 */
[0b10011] = 0x3f00, /* 1.75 */
[0b10100] = 0x4000, /* 2.0 */
[0b10101] = 0x4100, /* 2.5 */
[0b10110] = 0x4200, /* 3 */
[0b10111] = 0x4400, /* 4 */
[0b11000] = 0x4800, /* 8 */
[0b11001] = 0x4c00, /* 16 */
[0b11010] = 0x5800, /* 2^7 */
[0b11011] = 0x5c00, /* 2^8 */
[0b11100] = 0x7800, /* 2^15 */
[0b11101] = 0x7c00, /* +inf (2^16 is not expressible) */
[0b11110] = 0x7c00, /* +inf */
[0b11111] = defaultNaNF16UI
};
WRITE_FRD_H(f16(bits[insn.rs1()]));
}

46
riscv/insns/fli_q.h
View File

@ -0,0 +1,46 @@
require_extension('D');
require_extension(EXT_ZFA);
require_fp;
{
const uint64_t bits[32] = {
[0b00000] = 0xBFFF000000000000ull, /* -1.0 */
[0b00001] = 0x0001000000000000ull, /* minimum positive normal */
[0b00010] = 0x3FEF000000000000ull, /* 1.0 * 2^-16 */
[0b00011] = 0x3FF0000000000000ull, /* 1.0 * 2^-15 */
[0b00100] = 0x3FF7000000000000ull, /* 1.0 * 2^-8 */
[0b00101] = 0x3FF8000000000000ull, /* 1.0 * 2^-7 */
[0b00110] = 0x3FFB000000000000ull, /* 1.0 * 2^-4 */
[0b00111] = 0x3FF9000000000000ull, /* 1.0 * 2^-3 */
[0b01000] = 0x3FFD000000000000ull, /* 0.25 */
[0b01001] = 0x3FFD400000000000ull, /* 0.3125 */
[0b01010] = 0x3FFD800000000000ull, /* 0.375 */
[0b01011] = 0x3FFDC00000000000ull, /* 0.4375 */
[0b01100] = 0x3FFE000000000000ull, /* 0.5 */
[0b01101] = 0x3FFE400000000000ull, /* 0.625 */
[0b01110] = 0x3FFE800000000000ull, /* 0.75 */
[0b01111] = 0x3FFEC00000000000ull, /* 0.875 */
[0b10000] = 0x3FFF000000000000ull, /* 1.0 */
[0b10001] = 0x3FFF400000000000ull, /* 1.25 */
[0b10010] = 0x3FFFC00000000000ull, /* 1.5 */
[0b10011] = 0x4000000000000000ull, /* 1.75 */
[0b10100] = 0x4000400000000000ull, /* 2.0 */
[0b10101] = 0x4000800000000000ull, /* 2.5 */
[0b10110] = 0x4001000000000000ull, /* 3 */
[0b10111] = 0x4002000000000000ull, /* 4 */
[0b11000] = 0x4003000000000000ull, /* 8 */
[0b11001] = 0x400D000000000000ull, /* 16 */
[0b11010] = 0x4006000000000000ull, /* 2^7 */
[0b11011] = 0x4007000000000000ull, /* 2^8 */
[0b11100] = 0x400E000000000000ull, /* 2^15 */
[0b11101] = 0x400F000000000000ull, /* 2^16 */
[0b11110] = 0x7FFF000000000000ull, /* +inf */
[0b11111] = defaultNaNF128UI64
};
static_assert(defaultNaNF128UI0 == 0, "LSBs of quad-precision NaN must be zero");
ui128_f128 ui;
ui.ui.v64 = bits[insn.rs1()];
ui.ui.v0 = 0;
WRITE_FRD(f128(ui.f));
}

40
riscv/insns/fli_s.h
View File

@ -0,0 +1,40 @@
require_extension('F');
require_extension(EXT_ZFA);
require_fp;
{
const uint32_t bits[32] = {
[0b00000] = 0xbf800000, /* -1.0 */
[0b00001] = 0x00800000, /* minimum positive normal */
[0b00010] = 0x37800000, /* 1.0 * 2^-16 */
[0b00011] = 0x38000000, /* 1.0 * 2^-15 */
[0b00100] = 0x3b800000, /* 1.0 * 2^-8 */
[0b00101] = 0x3c000000, /* 1.0 * 2^-7 */
[0b00110] = 0x3d800000, /* 1.0 * 2^-4 */
[0b00111] = 0x3e000000, /* 1.0 * 2^-3 */
[0b01000] = 0x3e800000, /* 0.25 */
[0b01001] = 0x3ea00000, /* 0.3125 */
[0b01010] = 0x3ec00000, /* 0.375 */
[0b01011] = 0x3ee00000, /* 0.4375 */
[0b01100] = 0x3f000000, /* 0.5 */
[0b01101] = 0x3f200000, /* 0.625 */
[0b01110] = 0x3f400000, /* 0.75 */
[0b01111] = 0x3f600000, /* 0.875 */
[0b10000] = 0x3f800000, /* 1.0 */
[0b10001] = 0x3fa00000, /* 1.25 */
[0b10010] = 0x3fc00000, /* 1.5 */
[0b10011] = 0x3fe00000, /* 1.75 */
[0b10100] = 0x40000000, /* 2.0 */
[0b10101] = 0x40200000, /* 2.5 */
[0b10110] = 0x40400000, /* 3 */
[0b10111] = 0x40800000, /* 4 */
[0b11000] = 0x41000000, /* 8 */
[0b11001] = 0x41800000, /* 16 */
[0b11010] = 0x43000000, /* 2^7 */
[0b11011] = 0x43800000, /* 2^8 */
[0b11100] = 0x47000000, /* 2^15 */
[0b11101] = 0x47800000, /* 2^16 */
[0b11110] = 0x7f800000, /* +inf */
[0b11111] = defaultNaNF32UI
};
WRITE_FRD_F(f32(bits[insn.rs1()]));
}

4
riscv/insns/fltq_d.h
View File

@ -0,0 +1,4 @@
require_extension('D');
require_extension(EXT_ZFA);
require_fp;
WRITE_RD(f64_lt_quiet(FRS1_D, FRS2_D));

4
riscv/insns/fltq_h.h
View File

@ -0,0 +1,4 @@
require_extension(EXT_ZFH);
require_extension(EXT_ZFA);
require_fp;
WRITE_RD(f16_lt_quiet(FRS1_H, FRS2_H));

4
riscv/insns/fltq_q.h
View File

@ -0,0 +1,4 @@
require_extension('Q');
require_extension(EXT_ZFA);
require_fp;
WRITE_RD(f128_lt_quiet(f128(FRS1), f128(FRS2)));

4
riscv/insns/fltq_s.h
View File

@ -0,0 +1,4 @@
require_extension('F');
require_extension(EXT_ZFA);
require_fp;
WRITE_RD(f32_lt_quiet(FRS1_F, FRS2_F));

10
riscv/insns/fmaxm_d.h
View File

@ -0,0 +1,10 @@
require_extension('D');
require_extension(EXT_ZFA);
require_fp;
bool greater = f64_lt_quiet(FRS2_D, FRS1_D) ||
(f64_eq(FRS2_D, FRS1_D) && (FRS2_D.v & F64_SIGN));
if (isNaNF64UI(FRS1_D.v) || isNaNF64UI(FRS2_D.v))
WRITE_FRD_D(f64(defaultNaNF64UI));
else
WRITE_FRD_D(greater ? FRS1_D : FRS2_D);
set_fp_exceptions;

10
riscv/insns/fmaxm_h.h
View File

@ -0,0 +1,10 @@
require_extension(EXT_ZFH);
require_extension(EXT_ZFA);
require_fp;
bool greater = f16_lt_quiet(FRS2_H, FRS1_H) ||
(f16_eq(FRS2_H, FRS1_H) && (FRS2_H.v & F16_SIGN));
if (isNaNF16UI(FRS1_H.v) || isNaNF16UI(FRS2_H.v))
WRITE_FRD_H(f16(defaultNaNF16UI));
else
WRITE_FRD_H(greater ? FRS1_H : FRS2_H);
set_fp_exceptions;

17
riscv/insns/fmaxm_q.h
View File

@ -0,0 +1,17 @@
require_extension('D');
require_extension(EXT_ZFA);
require_fp;
ui128_f128 ui1;
ui1.f = f128(FRS1);
ui128_f128 ui2;
ui2.f = f128(FRS2);
bool greater = f128_lt_quiet(f128(FRS2), f128(FRS1)) ||
(f128_eq(f128(FRS1), f128(FRS2)) && (signF128UI64(ui2.ui.v64)));
if (isNaNF128UI(ui1.ui.v64, ui1.ui.v0) || isNaNF128UI(ui2.ui.v64, ui2.ui.v0)) {
ui128_f128 ui;
ui.ui.v64 = defaultNaNF128UI64;
ui.ui.v0 = defaultNaNF128UI0;
WRITE_FRD(f128(ui.f));
} else
WRITE_FRD(greater ? f128(FRS1) : f128(FRS2));
set_fp_exceptions;

10
riscv/insns/fmaxm_s.h
View File

@ -0,0 +1,10 @@
require_extension('F');
require_extension(EXT_ZFA);
require_fp;
bool greater = f32_lt_quiet(FRS2_F, FRS1_F) ||
(f32_eq(FRS2_F, FRS1_F) && (FRS2_F.v & F32_SIGN));
if (isNaNF32UI(FRS1_F.v) || isNaNF32UI(FRS2_F.v))
WRITE_FRD_F(f32(defaultNaNF32UI));
else
WRITE_FRD_F(greater ? FRS1_F : FRS2_F);
set_fp_exceptions;

10
riscv/insns/fminm_d.h
View File

@ -0,0 +1,10 @@
require_extension('D');
require_extension(EXT_ZFA);
require_fp;
bool less = f64_lt_quiet(FRS1_D, FRS2_D) ||
(f64_eq(FRS2_D, FRS1_D) && (FRS1_D.v & F64_SIGN));
if (isNaNF64UI(FRS1_D.v) || isNaNF64UI(FRS2_D.v))
WRITE_FRD_D(f64(defaultNaNF64UI));
else
WRITE_FRD_D(less ? FRS1_D : FRS2_D);
set_fp_exceptions;

10
riscv/insns/fminm_h.h
View File

@ -0,0 +1,10 @@
require_extension(EXT_ZFH);
require_extension(EXT_ZFA);
require_fp;
bool less = f16_lt_quiet(FRS1_H, FRS2_H) ||
(f16_eq(FRS2_H, FRS1_H) && (FRS1_H.v & F16_SIGN));
if (isNaNF16UI(FRS1_H.v) || isNaNF16UI(FRS2_H.v))
WRITE_FRD_H(f16(defaultNaNF16UI));
else
WRITE_FRD_H(less ? FRS1_H : FRS2_H);
set_fp_exceptions;

17
riscv/insns/fminm_q.h
View File

@ -0,0 +1,17 @@
require_extension('Q');
require_extension(EXT_ZFA);
require_fp;
ui128_f128 ui1;
ui1.f = f128(FRS1);
ui128_f128 ui2;
ui2.f = f128(FRS2);
bool less = f128_lt_quiet(f128(FRS1), f128(FRS2)) ||
(f128_eq(f128(FRS1), f128(FRS2)) && (signF128UI64(ui1.ui.v64)));
if (isNaNF128UI(ui1.ui.v64, ui1.ui.v0) || isNaNF128UI(ui2.ui.v64, ui2.ui.v0)) {
ui128_f128 ui;
ui.ui.v64 = defaultNaNF128UI64;
ui.ui.v0 = defaultNaNF128UI0;
WRITE_FRD(f128(ui.f));
} else
WRITE_FRD(less ? f128(FRS1) : f128(FRS2));
set_fp_exceptions;

10
riscv/insns/fminm_s.h
View File

@ -0,0 +1,10 @@
require_extension('F');
require_extension(EXT_ZFA);
require_fp;
bool less = f32_lt_quiet(FRS1_F, FRS2_F) ||
(f32_eq(FRS2_F, FRS1_F) && (FRS1_F.v & F32_SIGN));
if (isNaNF32UI(FRS1_F.v) || isNaNF32UI(FRS2_F.v))
WRITE_FRD_F(f32(defaultNaNF32UI));
else
WRITE_FRD_F(less ? FRS1_F : FRS2_F);
set_fp_exceptions;

7
riscv/insns/fmvh_x_d.h
View File

@ -0,0 +1,7 @@
require_rv32;
require_extension('D');
require_extension(EXT_ZFA);
require_fp;
ui64_f64 ui;
ui.f = FRS1_D;
WRITE_RD(ui.ui >> 32);

7
riscv/insns/fmvh_x_q.h
View File

@ -0,0 +1,7 @@
require_rv64;
require_extension('Q');
require_extension(EXT_ZFA);
require_fp;
ui128_f128 ui;
ui.f = f128(FRS1);
WRITE_RD(ui.ui.v64);

8
riscv/insns/fmvp_d_x.h
View File

@ -0,0 +1,8 @@
require_rv32;
require_extension('D');
require_extension(EXT_ZFA);
require_fp;
ui64_f64 ui;
ui.ui = ((uint64_t)RS2) << 32;
ui.ui |= RS1;
WRITE_FRD_D(f64(ui.ui));

8
riscv/insns/fmvp_q_x.h
View File

@ -0,0 +1,8 @@
require_rv64;
require_extension('Q');
require_extension(EXT_ZFA);
require_fp;
ui128_f128 ui;
ui.ui.v64 = RS2;
ui.ui.v0 = RS1;
WRITE_FRD(f128(ui.f));

5
riscv/insns/fround_d.h
View File

@ -0,0 +1,5 @@
require_extension('D');
require_extension(EXT_ZFA);
require_fp;
WRITE_FRD_D(f64_roundToInt(FRS1_D, RM, true));
set_fp_exceptions;

5
riscv/insns/fround_h.h
View File

@ -0,0 +1,5 @@
require_extension(EXT_ZFH);
require_extension(EXT_ZFA);
require_fp;
WRITE_FRD_H(f16_roundToInt(FRS1_H, RM, true));
set_fp_exceptions;

5
riscv/insns/fround_q.h
View File

@ -0,0 +1,5 @@
require_extension('Q');
require_extension(EXT_ZFA);
require_fp;
WRITE_FRD(f128_roundToInt(f128(FRS1), RM, true));
set_fp_exceptions;

5
riscv/insns/fround_s.h
View File

@ -0,0 +1,5 @@
require_extension('F');
require_extension(EXT_ZFA);
require_fp;
WRITE_FRD_F(f32_roundToInt(FRS1_F, RM, true));
set_fp_exceptions;

5
riscv/insns/froundnx_d.h
View File

@ -0,0 +1,5 @@
require_extension('D');
require_extension(EXT_ZFA);
require_fp;
WRITE_FRD_D(f64_roundToInt(FRS1_D, RM, false));
set_fp_exceptions;

5
riscv/insns/froundnx_h.h
View File

@ -0,0 +1,5 @@
require_extension(EXT_ZFH);
require_extension(EXT_ZFA);
require_fp;
WRITE_FRD_H(f16_roundToInt(FRS1_H, RM, false));
set_fp_exceptions;

5
riscv/insns/froundnx_q.h
View File

@ -0,0 +1,5 @@
require_extension('Q');
require_extension(EXT_ZFA);
require_fp;
WRITE_FRD(f128_roundToInt(f128(FRS1), RM, false));
set_fp_exceptions;

5
riscv/insns/froundnx_s.h
View File

@ -0,0 +1,5 @@
require_extension('F');
require_extension(EXT_ZFA);
require_fp;
WRITE_FRD_F(f32_roundToInt(FRS1_F, RM, false));
set_fp_exceptions;

2
riscv/isa_parser.cc
View File

@ -219,6 +219,8 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv)
extension_table[EXT_SVPBMT] = true;
} else if (ext_str == "svinval") {
extension_table[EXT_SVINVAL] = true;
} else if (ext_str == "zfa") {
extension_table[EXT_ZFA] = true;
} else if (ext_str == "zicbom") {
extension_table[EXT_ZICBOM] = true;
} else if (ext_str == "zicboz") {

1
riscv/isa_parser.h
View File

@ -48,6 +48,7 @@ typedef enum {
EXT_SVPBMT,
EXT_SVINVAL,
EXT_ZDINX,
EXT_ZFA,
EXT_ZFINX,
EXT_ZHINX,
EXT_ZHINXMIN,

45
riscv/riscv.mk.in
View File

@ -239,6 +239,15 @@ riscv_insn_ext_f = \
fsub_s \
fsw \
riscv_insn_ext_f_zfa= \
fli_s \
fmaxm_s \
fminm_s \
fround_s \
froundnx_s \
fleq_s \
fltq_s
riscv_insn_ext_d = \
fadd_d \
fclass_d \
@ -274,6 +283,18 @@ riscv_insn_ext_d = \
fsqrt_d \
fsub_d \
riscv_insn_ext_d_zfa = \
fli_d \
fmaxm_d \
fminm_d \
fround_d \
froundnx_d \
fmvh_x_d \
fmvp_d_x \
fcvtmod_w_d \
fleq_d \
fltq_d
riscv_insn_ext_zfh = \
fadd_h \
fclass_h \
@ -312,6 +333,15 @@ riscv_insn_ext_zfh = \
fsqrt_h \
fsub_h \
riscv_insn_ext_zfh_zfa = \
fli_h \
fmaxm_h \
fminm_h \
fround_h \
froundnx_h \
fleq_h \
fltq_h
riscv_insn_ext_q = \
fadd_q \
fclass_q \
@ -345,6 +375,17 @@ riscv_insn_ext_q = \
fsqrt_q \
fsub_q \
riscv_insn_ext_q_zfa = \
fli_q \
fmaxm_q \
fminm_q \
fround_q \
froundnx_q \
fmvh_x_q \
fmvp_q_x \
fleq_q \
fltq_q
riscv_insn_ext_b = \
add_uw \
andn \
@ -1321,9 +1362,13 @@ riscv_insn_list = \
$(riscv_insn_ext_i) \
$(riscv_insn_ext_m) \
$(riscv_insn_ext_f) \
$(riscv_insn_ext_f_zfa) \
$(riscv_insn_ext_d) \
$(riscv_insn_ext_d_zfa) \
$(riscv_insn_ext_zfh) \
$(riscv_insn_ext_zfh_zfa) \
$(riscv_insn_ext_q) \
$(riscv_insn_ext_q_zfa) \
$(riscv_insn_ext_b) \
$(riscv_insn_ext_k) \
$(if $(HAVE_INT128),$(riscv_insn_ext_v),) \

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