From da5866eac26eb90c9b2db17c79a4af0601743704 Mon Sep 17 00:00:00 2001 From: Scott Johnson Date: Mon, 22 Mar 2021 19:28:07 -0700 Subject: [PATCH] HS-level interrupts should always be enabled when in VS-mode See https://github.com/riscv/riscv-isa-manual/issues/633 --- riscv/processor.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv/processor.cc b/riscv/processor.cc index 2df049aa..0f7eadd2 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -562,7 +562,7 @@ void processor_t::take_interrupt(reg_t pending_interrupts) deleg = state.mideleg & ~state.hideleg; status = (state.v) ? state.vsstatus : state.mstatus; hsie = get_field(status, MSTATUS_SIE); - hs_enabled = state.prv < PRV_S || (state.prv == PRV_S && hsie); + hs_enabled = state.v || state.prv < PRV_S || (state.prv == PRV_S && hsie); enabled_interrupts = pending_interrupts & deleg & -hs_enabled; if (state.v && enabled_interrupts == 0) { // VS-ints have least priority and can only be taken with virt enabled