Simplify RV32 comparisons

No need to eliminate the upper 32 bits of the 64-bit x-register, as all
RV32 instructions should sign-extend their results to 64 bits.

riscv/decode.h

@@ -180,7 +180,6 @@ private:
 #endif
 #define require_accelerator if (unlikely((STATE.mstatus & MSTATUS_XS) == 0)) throw trap_illegal_instruction()
 
-#define cmp_trunc(reg) (reg_t(reg) << (64-xlen))
 #define set_fp_exceptions ({ STATE.fflags |= softfloat_exceptionFlags; \
                              softfloat_exceptionFlags = 0; })
 

riscv/insns/beq.h

@@ -1,2 +1,2 @@
-if(cmp_trunc(RS1) == cmp_trunc(RS2))
+if(RS1 == RS2)
   set_pc(BRANCH_TARGET);

riscv/insns/bge.h

@@ -1,2 +1,2 @@
-if(sreg_t(cmp_trunc(RS1)) >= sreg_t(cmp_trunc(RS2)))
+if(sreg_t(RS1) >= sreg_t(RS2))
   set_pc(BRANCH_TARGET);

riscv/insns/bgeu.h

@@ -1,2 +1,2 @@
-if(cmp_trunc(RS1) >= cmp_trunc(RS2))
+if(RS1 >= RS2)
   set_pc(BRANCH_TARGET);

riscv/insns/blt.h

@@ -1,2 +1,2 @@
-if(sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2)))
+if(sreg_t(RS1) < sreg_t(RS2))
   set_pc(BRANCH_TARGET);

riscv/insns/bltu.h

@@ -1,2 +1,2 @@
-if(cmp_trunc(RS1) < cmp_trunc(RS2))
+if(RS1 < RS2)
   set_pc(BRANCH_TARGET);

riscv/insns/bne.h

@@ -1,2 +1,2 @@
-if(cmp_trunc(RS1) != cmp_trunc(RS2))
+if(RS1 != RS2)
   set_pc(BRANCH_TARGET);

riscv/insns/slt.h

@@ -1 +1 @@
-WRITE_RD(sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2)));
+WRITE_RD(sreg_t(RS1) < sreg_t(RS2));

riscv/insns/slti.h

@@ -1 +1 @@
-WRITE_RD(sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(insn.i_imm())));
+WRITE_RD(sreg_t(RS1) < sreg_t(insn.i_imm()));

riscv/insns/sltiu.h

@@ -1 +1 @@
-WRITE_RD(cmp_trunc(RS1) < cmp_trunc(insn.i_imm()));
+WRITE_RD(RS1 < insn.i_imm());

riscv/insns/sltu.h

@@ -1 +1 @@
-WRITE_RD(cmp_trunc(RS1) < cmp_trunc(RS2));
+WRITE_RD(RS1 < RS2);