From d92df7049b140688ec8a2d6ec381a524c50ac585 Mon Sep 17 00:00:00 2001
From: Scott Johnson <scott.johnson@arilinc.com>
Date: Sat, 13 Nov 2021 08:56:39 -0800
Subject: [PATCH] Simplify calculation of VS-mode delegation

Since hideleg is now masked by mideleg, there's no need to separately
consider mideleg here.
---
 riscv/processor.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 24338056..4f0b8aae 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -736,7 +736,7 @@ void processor_t::take_interrupt(reg_t pending_interrupts)
     enabled_interrupts = pending_interrupts & deleg_to_hs & -hs_enabled;
     if (state.v && enabled_interrupts == 0) {
       // VS-ints have least priority and can only be taken with virt enabled
-      const reg_t deleg_to_vs = state.mideleg->read() & state.hideleg->read();
+      const reg_t deleg_to_vs = state.hideleg->read();
       const reg_t vs_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
       enabled_interrupts = pending_interrupts & deleg_to_vs & -vs_enabled;
     }
@@ -867,7 +867,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
   bool curr_virt = state.v;
   bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0;
   if (interrupt) {
-    vsdeleg = (curr_virt && state.prv <= PRV_S) ? (state.mideleg->read() & state.hideleg->read()) : 0;
+    vsdeleg = (curr_virt && state.prv <= PRV_S) ? state.hideleg->read() : 0;
     hsdeleg = (state.prv <= PRV_S) ? state.mideleg->read() : 0;
     bit &= ~((reg_t)1 << (max_xlen-1));
   } else {