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Simplify calculation of VS-mode delegation
Since hideleg is now masked by mideleg, there's no need to separately
consider mideleg here.
pull/859/head
Scott Johnson
5 years ago
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GPG Key ID: 61C1F01D3D1410C9
1 changed files with
2 additions and
2 deletions
-
riscv/processor.cc
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@ -736,7 +736,7 @@ void processor_t::take_interrupt(reg_t pending_interrupts) |
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enabled_interrupts = pending_interrupts & deleg_to_hs & -hs_enabled; |
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if (state.v && enabled_interrupts == 0) { |
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// VS-ints have least priority and can only be taken with virt enabled
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const reg_t deleg_to_vs = state.mideleg->read() & state.hideleg->read(); |
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const reg_t deleg_to_vs = state.hideleg->read(); |
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const reg_t vs_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie); |
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enabled_interrupts = pending_interrupts & deleg_to_vs & -vs_enabled; |
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} |
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@ -867,7 +867,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc) |
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bool curr_virt = state.v; |
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bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0; |
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if (interrupt) { |
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vsdeleg = (curr_virt && state.prv <= PRV_S) ? (state.mideleg->read() & state.hideleg->read()) : 0; |
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vsdeleg = (curr_virt && state.prv <= PRV_S) ? state.hideleg->read() : 0; |
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hsdeleg = (state.prv <= PRV_S) ? state.mideleg->read() : 0; |
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bit &= ~((reg_t)1 << (max_xlen-1)); |
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} else { |
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