diff --git a/riscv/insns/vclmul_vv.h b/riscv/insns/vclmul_vv.h
new file mode 100644
index 00000000..8957738a
--- /dev/null
+++ b/riscv/insns/vclmul_vv.h
@@ -0,0 +1,20 @@
+// vclmul.vv vd, vs2, vs1, vm
+
+#include "zvk_ext_macros.h"
+
+require_zvbc;
+require(P.VU.vsew == 64);
+
+VI_VV_ULOOP
+({
+  // Perform a carryless multiplication 64bx64b on each 64b element,
+  // return the low 64b of the 128b product.
+  //   <https://en.wikipedia.org/wiki/Carry-less_product>
+  vd = 0;
+  for (std::size_t bit_idx = 0; bit_idx < sew; ++bit_idx) {
+    const reg_t mask = ((reg_t) 1) << bit_idx;
+    if ((vs1 & mask) != 0) {
+      vd ^= vs2 << bit_idx;
+    }
+  }
+})
diff --git a/riscv/insns/vclmul_vx.h b/riscv/insns/vclmul_vx.h
new file mode 100644
index 00000000..1df7a3a2
--- /dev/null
+++ b/riscv/insns/vclmul_vx.h
@@ -0,0 +1,20 @@
+// vclmul.vx vd, vs2, rs1, vm
+
+#include "zvk_ext_macros.h"
+
+require_zvbc;
+require(P.VU.vsew == 64);
+
+VI_VX_ULOOP
+({
+  // Perform a carryless multiplication 64bx64b on each 64b element,
+  // return the low 64b of the 128b product.
+  //   <https://en.wikipedia.org/wiki/Carry-less_product>
+  vd = 0;
+  for (std::size_t bit_idx = 0; bit_idx < sew; ++bit_idx) {
+    const reg_t mask = ((reg_t) 1) << bit_idx;
+    if ((rs1 & mask) != 0) {
+        vd ^= vs2 << bit_idx;
+    }
+  }
+})
diff --git a/riscv/insns/vclmulh_vv.h b/riscv/insns/vclmulh_vv.h
new file mode 100644
index 00000000..6a54bcfa
--- /dev/null
+++ b/riscv/insns/vclmulh_vv.h
@@ -0,0 +1,20 @@
+// vclmulh.vv vd, vs2, vs1, vm
+
+#include "zvk_ext_macros.h"
+
+require_zvbc;
+require(P.VU.vsew == 64);
+
+VI_VV_ULOOP
+({
+  // Perform a carryless multiplication 64bx64b on each 64b element,
+  // return the high 64b of the 128b product.
+  //   <https://en.wikipedia.org/wiki/Carry-less_product>
+  vd = 0;
+  for (std::size_t bit_idx = 1; bit_idx < sew; ++bit_idx) {
+    const reg_t mask = ((reg_t) 1) << bit_idx;
+    if ((vs1 & mask) != 0) {
+      vd ^= ((reg_t)vs2) >> (sew - bit_idx);
+    }
+  }
+})
diff --git a/riscv/insns/vclmulh_vx.h b/riscv/insns/vclmulh_vx.h
new file mode 100644
index 00000000..e874d1df
--- /dev/null
+++ b/riscv/insns/vclmulh_vx.h
@@ -0,0 +1,20 @@
+// vclmulh.vx vd, vs2, rs1, vm
+
+#include "zvk_ext_macros.h"
+
+require_zvbc;
+require(P.VU.vsew == 64);
+
+VI_VX_ULOOP
+({
+  // Perform a carryless multiplication 64bx64b on each 64b element,
+  // return the high 64b of the 128b product.
+  //   <https://en.wikipedia.org/wiki/Carry-less_product>
+  vd = 0;
+  for (std::size_t bit_idx = 1; bit_idx < sew; ++bit_idx) {
+    const reg_t mask = ((reg_t) 1) << bit_idx;
+    if ((rs1 & mask) != 0) {
+      vd ^= ((reg_t)vs2) >> (sew - bit_idx);
+    }
+  }
+})
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 4aa23e3c..dcf26406 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -1358,8 +1358,15 @@ riscv_insn_ext_zvbb = \
 	vwsll_vv \
 	vwsll_vx \
 
+riscv_insn_ext_zvbc = \
+	vclmul_vv \
+	vclmul_vx \
+	vclmulh_vv \
+	vclmulh_vx \
+
 riscv_insn_ext_zvk = \
 	$(riscv_insn_ext_zvbb) \
+	$(riscv_insn_ext_zvbc) \
 
 riscv_insn_list = \
 	$(if $(HAVE_INT128),$(riscv_insn_ext_v),) \