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Brief: - This commit adds spike support for the scalar cryptography extension. See the riscv-crypto repository (https://github.com/riscv/riscv-crypto) for more information on this extension. - It is based on the experimental patch which has so far been kept in the riscv-crypto repository. Now that scalar crypto is nearly at the "freeze" stage and entering opcode consistency review, it makes sense to start upstreaming our experimental version. - In terms of compiler support - we are using an experimental patch in the riscv-crypto repository at the moment, others are working on an upstream appropriate version. Details: - Add support for dedicated scalar crypto instructions. - Add very basic support for the entropy source (entropy_source.h). Much of the behaviour of this is implementation specific. This model aims to provide the bare minimum of functionality which can be used to quickly develop software. It uses /dev/urandom as its entropy source for now. - Scalar crypto is unique in that it _borrows_ instructions from the Bitmanipulation extension. This is currently _not_ encoded in the patch, as I didn't want to damage anything in Bitmanip which is currently under review. However, I've added a macro in riscv/decode.h called "require_either_extension(A,B)", which allows instructions to be valid opcodes iff they are in one or both extensions. On branch scalar-crypto Changes to be committed: modified: README.md modified: riscv/decode.h modified: riscv/encoding.h new file: riscv/entropy_source.h new file: riscv/insns/aes64im.h new file: riscv/insns/aes64ks1i.h new file: riscv/insns/aes64ks2.h new file: riscv/insns/aes_common.h new file: riscv/insns/aesds.h new file: riscv/insns/aesdsm.h new file: riscv/insns/aeses.h new file: riscv/insns/aesesm.h new file: riscv/insns/sha256sig0.h new file: riscv/insns/sha256sig1.h new file: riscv/insns/sha256sum0.h new file: riscv/insns/sha256sum1.h new file: riscv/insns/sha512sig0.h new file: riscv/insns/sha512sig0h.h new file: riscv/insns/sha512sig0l.h new file: riscv/insns/sha512sig1.h new file: riscv/insns/sha512sig1h.h new file: riscv/insns/sha512sig1l.h new file: riscv/insns/sha512sum0.h new file: riscv/insns/sha512sum0r.h new file: riscv/insns/sha512sum1.h new file: riscv/insns/sha512sum1r.h new file: riscv/insns/sm3p0.h new file: riscv/insns/sm3p1.h new file: riscv/insns/sm4_common.h new file: riscv/insns/sm4ed.h new file: riscv/insns/sm4ks.h modified: riscv/processor.cc modified: riscv/processor.h modified: riscv/riscv.mk.inpull/480/merge
Ben Marshall
5 years ago
committed by
GitHub
GitHub
34 changed files with 984 additions and 1 deletions
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#include <fstream> |
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#include <iostream> |
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#include "internals.h" |
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//
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// Used to model the cryptography extension entropy source.
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// See Section 4 of the Scalar Cryptography Extension specificaiton.
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class entropy_source { |
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public: |
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// Valid return codes for OPST bits [31:30] when reading mentropy.
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static const uint32_t OPST_BIST = 0x0 << 30; |
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static const uint32_t OPST_ES16 = 0x1 << 30; |
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static const uint32_t OPST_WAIT = 0x2 << 30; |
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static const uint32_t OPST_DEAD = 0x3 << 30; |
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//
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// Other system events
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// ------------------------------------------------------------
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void reset() { |
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// Does nothing for now. In the future, can be used to model things
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// like initial BIST states.
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} |
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//
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// mentropy register
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// ------------------------------------------------------------
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void set_mentropy(reg_t val) { |
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// Always ignore writes to mentropy.
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// This CSR *must never* accept write values, it is strictly read only.
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} |
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//
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// The format of mentropy is described in Table 3 / Section 4.1 of
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// the scalar cryptography specification.
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reg_t get_mentropy() { |
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uint32_t result = 0; |
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// Currently, always return ES16 (i.e. good randomness) unless in
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// noise capture mode. In the future, we can more realistically model
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// things like WAIT states, BIST warm up and maybe scriptable entry
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// into the DEAD state, but until then, this is the bare minimum.
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uint32_t return_status = noise_capture_mode ? OPST_BIST : OPST_ES16; |
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if(return_status == OPST_ES16) { |
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// Add some sampled entropy into the low 16 bits
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uint16_t seed = this -> get_two_random_bytes(); |
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result |= seed; |
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} else if(return_status == OPST_BIST) { |
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// Do nothing.
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} else if(return_status == OPST_WAIT) { |
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// Do nothing.
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} else if(return_status == OPST_DEAD) { |
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// Do nothing. Stay dead.
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} else { |
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// Unreachable.
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} |
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// Note that if we get here any return_status is anything other than
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// OPST_ES16, then the low 16-bits of the return value must be zero.
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result |= return_status; |
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// Result is zero-extended on RV64.
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return (reg_t)result; |
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} |
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//
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// mnoise register
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// ------------------------------------------------------------
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void set_mnoise(reg_t val) { |
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// Almost all of the behaviour for mnoise is vendor specific,
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// except for bit 31.
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int new_noisemode = (val >> 31) & 0x1; |
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noise_capture_mode = new_noisemode == 1; |
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} |
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reg_t get_mnoise() { |
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reg_t to_return = 0; |
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if(this -> noise_capture_mode) { |
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// Set bit 31 indicating we are in noise capture mode.
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to_return |= 0x1 << 31; |
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} |
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return to_return; |
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} |
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//
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// Utility / support variables and functions.
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// ------------------------------------------------------------
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// The ES is in noise capture mode?
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// If so, then get_mentropy must always return OPST_BIST.
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bool noise_capture_mode = false; |
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// The file to read entropy from.
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std::string randomness_source = "/dev/urandom"; |
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// Read two random bytes from the entropy source file.
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uint16_t get_two_random_bytes() { |
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std::ifstream fh(this -> randomness_source, std::ios::binary); |
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if(fh.is_open()) { |
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uint16_t random_bytes; |
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fh.read((char*)(&random_bytes), 2); |
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fh.close(); |
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return random_bytes; |
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} else { |
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fprintf(stderr, "Could not open randomness source file:\n\t"); |
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fprintf(stderr, "%s", randomness_source.c_str()); |
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abort(); |
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} |
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} |
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}; |
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@ -0,0 +1,16 @@ |
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#include "aes_common.h" |
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require_rv64; |
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require_extension('K'); |
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uint32_t col_0 = RS1 & 0xFFFFFFFF; |
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uint32_t col_1 = RS1 >> 32 ; |
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col_0 = AES_INVMIXCOLUMN(col_0); |
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col_1 = AES_INVMIXCOLUMN(col_1); |
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uint64_t result= ((uint64_t)col_1 << 32) | col_0; |
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WRITE_RD(result); |
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@ -0,0 +1,38 @@ |
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#include "aes_common.h" |
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require_rv64; |
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require_extension('K'); |
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uint8_t round_consts [10] = { |
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0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36 |
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}; |
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uint8_t enc_rcon = insn.rcon() ; |
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if(enc_rcon > 0xA) { |
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// Invalid opcode.
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throw trap_illegal_instruction(0); |
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} |
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uint32_t temp = (RS1 >> 32) & 0xFFFFFFFF ; |
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uint8_t rcon = 0 ; |
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uint64_t result ; |
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if(enc_rcon != 0xA) { |
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temp = (temp >> 8) | (temp << 24); // Rotate left by 8
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rcon = round_consts[enc_rcon]; |
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} |
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temp = |
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((uint32_t)AES_ENC_SBOX[(temp >> 24) & 0xFF] << 24) | |
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((uint32_t)AES_ENC_SBOX[(temp >> 16) & 0xFF] << 16) | |
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((uint32_t)AES_ENC_SBOX[(temp >> 8) & 0xFF] << 8) | |
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((uint32_t)AES_ENC_SBOX[(temp >> 0) & 0xFF] << 0) ; |
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temp ^= rcon; |
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result = ((uint64_t)temp << 32) | temp; |
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WRITE_RD(result); |
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@ -0,0 +1,16 @@ |
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#include "aes_common.h" |
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require_rv64; |
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require_extension('K'); |
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uint32_t rs1_hi = RS1 >> 32; |
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uint32_t rs2_lo = RS2 ; |
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uint32_t rs2_hi = RS2 >> 32; |
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uint32_t r_lo = (rs1_hi ^ rs2_lo ) ; |
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uint32_t r_hi = (rs1_hi ^ rs2_lo ^ rs2_hi) ; |
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uint64_t result = ((uint64_t)r_hi << 32) | r_lo ; |
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WRITE_RD(result); |
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@ -0,0 +1,156 @@ |
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uint8_t AES_ENC_SBOX[]= { |
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0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5, |
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0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76, |
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0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, 0x47, 0xF0, |
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0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0, |
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0xB7, 0xFD, 0x93, 0x26, 0x36, 0x3F, 0xF7, 0xCC, |
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0x34, 0xA5, 0xE5, 0xF1, 0x71, 0xD8, 0x31, 0x15, |
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0x04, 0xC7, 0x23, 0xC3, 0x18, 0x96, 0x05, 0x9A, |
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0x07, 0x12, 0x80, 0xE2, 0xEB, 0x27, 0xB2, 0x75, |
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0x09, 0x83, 0x2C, 0x1A, 0x1B, 0x6E, 0x5A, 0xA0, |
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0x52, 0x3B, 0xD6, 0xB3, 0x29, 0xE3, 0x2F, 0x84, |
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0x53, 0xD1, 0x00, 0xED, 0x20, 0xFC, 0xB1, 0x5B, |
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0x6A, 0xCB, 0xBE, 0x39, 0x4A, 0x4C, 0x58, 0xCF, |
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0xD0, 0xEF, 0xAA, 0xFB, 0x43, 0x4D, 0x33, 0x85, |
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0x45, 0xF9, 0x02, 0x7F, 0x50, 0x3C, 0x9F, 0xA8, |
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0x51, 0xA3, 0x40, 0x8F, 0x92, 0x9D, 0x38, 0xF5, |
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0xBC, 0xB6, 0xDA, 0x21, 0x10, 0xFF, 0xF3, 0xD2, |
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0xCD, 0x0C, 0x13, 0xEC, 0x5F, 0x97, 0x44, 0x17, |
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0xC4, 0xA7, 0x7E, 0x3D, 0x64, 0x5D, 0x19, 0x73, |
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0x60, 0x81, 0x4F, 0xDC, 0x22, 0x2A, 0x90, 0x88, |
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0x46, 0xEE, 0xB8, 0x14, 0xDE, 0x5E, 0x0B, 0xDB, |
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0xE0, 0x32, 0x3A, 0x0A, 0x49, 0x06, 0x24, 0x5C, |
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0xC2, 0xD3, 0xAC, 0x62, 0x91, 0x95, 0xE4, 0x79, |
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0xE7, 0xC8, 0x37, 0x6D, 0x8D, 0xD5, 0x4E, 0xA9, |
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0x6C, 0x56, 0xF4, 0xEA, 0x65, 0x7A, 0xAE, 0x08, |
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0xBA, 0x78, 0x25, 0x2E, 0x1C, 0xA6, 0xB4, 0xC6, |
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0xE8, 0xDD, 0x74, 0x1F, 0x4B, 0xBD, 0x8B, 0x8A, |
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0x70, 0x3E, 0xB5, 0x66, 0x48, 0x03, 0xF6, 0x0E, |
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0x61, 0x35, 0x57, 0xB9, 0x86, 0xC1, 0x1D, 0x9E, |
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0xE1, 0xF8, 0x98, 0x11, 0x69, 0xD9, 0x8E, 0x94, |
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0x9B, 0x1E, 0x87, 0xE9, 0xCE, 0x55, 0x28, 0xDF, |
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0x8C, 0xA1, 0x89, 0x0D, 0xBF, 0xE6, 0x42, 0x68, |
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0x41, 0x99, 0x2D, 0x0F, 0xB0, 0x54, 0xBB, 0x16 |
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}; |
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uint8_t AES_DEC_SBOX[] = { |
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0x52, 0x09, 0x6A, 0xD5, 0x30, 0x36, 0xA5, 0x38, |
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0xBF, 0x40, 0xA3, 0x9E, 0x81, 0xF3, 0xD7, 0xFB, |
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0x7C, 0xE3, 0x39, 0x82, 0x9B, 0x2F, 0xFF, 0x87, |
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0x34, 0x8E, 0x43, 0x44, 0xC4, 0xDE, 0xE9, 0xCB, |
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0x54, 0x7B, 0x94, 0x32, 0xA6, 0xC2, 0x23, 0x3D, |
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0xEE, 0x4C, 0x95, 0x0B, 0x42, 0xFA, 0xC3, 0x4E, |
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0x08, 0x2E, 0xA1, 0x66, 0x28, 0xD9, 0x24, 0xB2, |
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0x76, 0x5B, 0xA2, 0x49, 0x6D, 0x8B, 0xD1, 0x25, |
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0x72, 0xF8, 0xF6, 0x64, 0x86, 0x68, 0x98, 0x16, |
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0xD4, 0xA4, 0x5C, 0xCC, 0x5D, 0x65, 0xB6, 0x92, |
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0x6C, 0x70, 0x48, 0x50, 0xFD, 0xED, 0xB9, 0xDA, |
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0x5E, 0x15, 0x46, 0x57, 0xA7, 0x8D, 0x9D, 0x84, |
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0x90, 0xD8, 0xAB, 0x00, 0x8C, 0xBC, 0xD3, 0x0A, |
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0xF7, 0xE4, 0x58, 0x05, 0xB8, 0xB3, 0x45, 0x06, |
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0xD0, 0x2C, 0x1E, 0x8F, 0xCA, 0x3F, 0x0F, 0x02, |
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0xC1, 0xAF, 0xBD, 0x03, 0x01, 0x13, 0x8A, 0x6B, |
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0x3A, 0x91, 0x11, 0x41, 0x4F, 0x67, 0xDC, 0xEA, |
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0x97, 0xF2, 0xCF, 0xCE, 0xF0, 0xB4, 0xE6, 0x73, |
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0x96, 0xAC, 0x74, 0x22, 0xE7, 0xAD, 0x35, 0x85, |
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0xE2, 0xF9, 0x37, 0xE8, 0x1C, 0x75, 0xDF, 0x6E, |
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0x47, 0xF1, 0x1A, 0x71, 0x1D, 0x29, 0xC5, 0x89, |
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0x6F, 0xB7, 0x62, 0x0E, 0xAA, 0x18, 0xBE, 0x1B, |
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0xFC, 0x56, 0x3E, 0x4B, 0xC6, 0xD2, 0x79, 0x20, |
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0x9A, 0xDB, 0xC0, 0xFE, 0x78, 0xCD, 0x5A, 0xF4, |
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0x1F, 0xDD, 0xA8, 0x33, 0x88, 0x07, 0xC7, 0x31, |
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0xB1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xEC, 0x5F, |
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0x60, 0x51, 0x7F, 0xA9, 0x19, 0xB5, 0x4A, 0x0D, |
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0x2D, 0xE5, 0x7A, 0x9F, 0x93, 0xC9, 0x9C, 0xEF, |
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0xA0, 0xE0, 0x3B, 0x4D, 0xAE, 0x2A, 0xF5, 0xB0, |
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0xC8, 0xEB, 0xBB, 0x3C, 0x83, 0x53, 0x99, 0x61, |
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0x17, 0x2B, 0x04, 0x7E, 0xBA, 0x77, 0xD6, 0x26, |
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0xE1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0C, 0x7D |
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}; |
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#define AES_UNPACK_BYTES(b0,b1,b2,b3) \ |
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uint8_t b0 = (RS1 >> 0) & 0xFF; \ |
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uint8_t b1 = (RS2 >> 8) & 0xFF; \ |
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uint8_t b2 = (RS1 >> 16) & 0xFF; \ |
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uint8_t b3 = (RS2 >> 24) & 0xFF; \ |
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#define AES_PACK_BYTES(b0,b1,b2,b3) ( \ |
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(uint32_t)b0 << 0 | \ |
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(uint32_t)b1 << 8 | \ |
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(uint32_t)b2 << 16 | \ |
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(uint32_t)b3 << 24 ) |
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#define AES_SBOX(b0, b1, b2, b3) \ |
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b0 = AES_ENC_SBOX[b0]; \ |
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b1 = AES_ENC_SBOX[b1]; \ |
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b2 = AES_ENC_SBOX[b2]; \ |
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b3 = AES_ENC_SBOX[b3]; \ |
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#define AES_RSBOX(b0, b1, b2, b3) \ |
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b0 = AES_DEC_SBOX[b0]; \ |
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b1 = AES_DEC_SBOX[b1]; \ |
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b2 = AES_DEC_SBOX[b2]; \ |
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b3 = AES_DEC_SBOX[b3]; \ |
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#define AES_XTIME(a) \ |
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((a << 1) ^ ((a&0x80) ? 0x1b : 0)) |
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#define AES_GFMUL(a,b) (( \ |
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( ( (b) & 0x1 ) ? (a) : 0 ) ^ \ |
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( ( (b) & 0x2 ) ? AES_XTIME(a) : 0 ) ^ \ |
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( ( (b) & 0x4 ) ? AES_XTIME(AES_XTIME(a)) : 0 ) ^ \ |
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( ( (b) & 0x8 ) ? AES_XTIME(AES_XTIME(AES_XTIME(a))) : 0 ) )&0xFF) |
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#define BY(X,I) ((X >> (8*I)) & 0xFF) |
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#define AES_SHIFROWS_LO(RS1,RS2) ( \ |
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(((RS1 >> 24) & 0xFF) << 56) | \ |
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(((RS2 >> 48) & 0xFF) << 48) | \ |
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(((RS2 >> 8) & 0xFF) << 40) | \ |
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(((RS1 >> 32) & 0xFF) << 32) | \ |
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(((RS2 >> 56) & 0xFF) << 24) | \ |
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(((RS2 >> 16) & 0xFF) << 16) | \ |
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(((RS1 >> 40) & 0xFF) << 8) | \ |
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(((RS1 >> 0) & 0xFF) << 0) ) |
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#define AES_INVSHIFROWS_LO(RS1,RS2) ( \ |
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(((RS2 >> 24) & 0xFF) << 56) | \ |
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(((RS2 >> 48) & 0xFF) << 48) | \ |
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(((RS1 >> 8) & 0xFF) << 40) | \ |
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(((RS1 >> 32) & 0xFF) << 32) | \ |
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(((RS1 >> 56) & 0xFF) << 24) | \ |
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(((RS2 >> 16) & 0xFF) << 16) | \ |
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(((RS2 >> 40) & 0xFF) << 8) | \ |
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(((RS1 >> 0) & 0xFF) << 0) ) |
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#define AES_MIXBYTE(COL,B0,B1,B2,B3) ( \ |
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BY(COL,B3) ^ \ |
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BY(COL,B2) ^ \ |
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AES_GFMUL(BY(COL,B1), 3) ^ \ |
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AES_GFMUL(BY(COL,B0), 2) \ |
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) |
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#define AES_MIXCOLUMN(COL) ( \ |
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AES_MIXBYTE(COL,3,0,1,2) << 24 | \ |
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AES_MIXBYTE(COL,2,3,0,1) << 16 | \ |
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AES_MIXBYTE(COL,1,2,3,0) << 8 | \ |
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AES_MIXBYTE(COL,0,1,2,3) << 0 \ |
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) |
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#define AES_INVMIXBYTE(COL,B0,B1,B2,B3) ( \ |
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AES_GFMUL(BY(COL,B3),0x9) ^ \ |
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AES_GFMUL(BY(COL,B2),0xd) ^ \ |
|||
AES_GFMUL(BY(COL,B1),0xb) ^ \ |
|||
AES_GFMUL(BY(COL,B0),0xe) \ |
|||
) |
|||
|
|||
#define AES_INVMIXCOLUMN(COL) ( \ |
|||
AES_INVMIXBYTE(COL,3,0,1,2) << 24 | \ |
|||
AES_INVMIXBYTE(COL,2,3,0,1) << 16 | \ |
|||
AES_INVMIXBYTE(COL,1,2,3,0) << 8 | \ |
|||
AES_INVMIXBYTE(COL,0,1,2,3) << 0 \ |
|||
) |
|||
|
|||
@ -0,0 +1,47 @@ |
|||
|
|||
#include "aes_common.h" |
|||
|
|||
// The encodings for the RV32 and RV64 AES instructions overlap, as they
|
|||
// are mutually exclusive. They have rather different functionality.
|
|||
|
|||
if(xlen == 32) { |
|||
// Execute the RV32 aes32dsi instruction
|
|||
|
|||
require_rv32; |
|||
require_extension('K'); |
|||
require(RD == 0); // Additional decoding required for RV32
|
|||
|
|||
uint8_t bs = insn.bs(); |
|||
|
|||
uint8_t t0 = RS2 >> (8*bs); |
|||
uint8_t x = AES_DEC_SBOX[t0]; |
|||
uint32_t u = x; |
|||
|
|||
u = (u << (8*bs)) | (u >> (32-8*bs)); |
|||
|
|||
uint64_t rd = insn.rs1(); // RD sourced from RS1 field.
|
|||
WRITE_REG(rd, u ^ RS1); |
|||
|
|||
} else { |
|||
// Execute the RV64 aes64ds instruction
|
|||
|
|||
require(insn.bs() == 0); |
|||
require_rv64; |
|||
require_extension('K'); |
|||
|
|||
uint64_t temp = AES_INVSHIFROWS_LO(RS1,RS2); |
|||
|
|||
temp = ( |
|||
((uint64_t)AES_DEC_SBOX[(temp >> 0) & 0xFF] << 0) | |
|||
((uint64_t)AES_DEC_SBOX[(temp >> 8) & 0xFF] << 8) | |
|||
((uint64_t)AES_DEC_SBOX[(temp >> 16) & 0xFF] << 16) | |
|||
((uint64_t)AES_DEC_SBOX[(temp >> 24) & 0xFF] << 24) | |
|||
((uint64_t)AES_DEC_SBOX[(temp >> 32) & 0xFF] << 32) | |
|||
((uint64_t)AES_DEC_SBOX[(temp >> 40) & 0xFF] << 40) | |
|||
((uint64_t)AES_DEC_SBOX[(temp >> 48) & 0xFF] << 48) | |
|||
((uint64_t)AES_DEC_SBOX[(temp >> 56) & 0xFF] << 56) |
|||
); |
|||
|
|||
WRITE_RD(temp); |
|||
|
|||
} |
|||
@ -0,0 +1,60 @@ |
|||
|
|||
#include "aes_common.h" |
|||
|
|||
// The encodings for the RV32 and RV64 AES instructions overlap, as they
|
|||
// are mutually exclusive. They have rather different functionality.
|
|||
|
|||
if(xlen == 32) { |
|||
// Execute the RV32 aes32dsmi instruction
|
|||
|
|||
require_rv32; |
|||
require_extension('K'); |
|||
require(RD == 0); // Additional decoding required for RV32
|
|||
|
|||
uint8_t bs = insn.bs(); |
|||
|
|||
uint8_t t0 = RS2 >> (8*bs); |
|||
uint8_t x = AES_DEC_SBOX[t0]; |
|||
uint32_t u ; |
|||
|
|||
u = (AES_GFMUL(x,0xb) << 24) | |
|||
(AES_GFMUL(x,0xd) << 16) | |
|||
(AES_GFMUL(x,0x9) << 8) | |
|||
(AES_GFMUL(x,0xe) << 0) ; |
|||
|
|||
u = (u << (8*bs)) | (u >> (32-8*bs)); |
|||
|
|||
uint64_t rd = insn.rs1(); // RD sourced from RS1 field.
|
|||
WRITE_REG(rd, u ^ RS1); |
|||
|
|||
} else { |
|||
// Execute the RV64 aes64dsm instruction
|
|||
|
|||
require(insn.bs() == 0); |
|||
require_rv64; |
|||
require_extension('K'); |
|||
|
|||
uint64_t temp = AES_INVSHIFROWS_LO(RS1,RS2); |
|||
|
|||
temp = ( |
|||
((uint64_t)AES_DEC_SBOX[(temp >> 0) & 0xFF] << 0) | |
|||
((uint64_t)AES_DEC_SBOX[(temp >> 8) & 0xFF] << 8) | |
|||
((uint64_t)AES_DEC_SBOX[(temp >> 16) & 0xFF] << 16) | |
|||
((uint64_t)AES_DEC_SBOX[(temp >> 24) & 0xFF] << 24) | |
|||
((uint64_t)AES_DEC_SBOX[(temp >> 32) & 0xFF] << 32) | |
|||
((uint64_t)AES_DEC_SBOX[(temp >> 40) & 0xFF] << 40) | |
|||
((uint64_t)AES_DEC_SBOX[(temp >> 48) & 0xFF] << 48) | |
|||
((uint64_t)AES_DEC_SBOX[(temp >> 56) & 0xFF] << 56) |
|||
); |
|||
|
|||
uint32_t col_0 = temp & 0xFFFFFFFF; |
|||
uint32_t col_1 = temp >> 32 ; |
|||
|
|||
col_0 = AES_INVMIXCOLUMN(col_0); |
|||
col_1 = AES_INVMIXCOLUMN(col_1); |
|||
|
|||
uint64_t result= ((uint64_t)col_1 << 32) | col_0; |
|||
|
|||
WRITE_RD(result); |
|||
|
|||
} |
|||
@ -0,0 +1,47 @@ |
|||
|
|||
#include "aes_common.h" |
|||
|
|||
// The encodings for the RV32 and RV64 AES instructions overlap, as they
|
|||
// are mutually exclusive. They have rather different functionality.
|
|||
|
|||
if(xlen == 32) { |
|||
// Execute the RV32 aes32esi instruction
|
|||
|
|||
require_rv32; |
|||
require_extension('K'); |
|||
require(RD == 0); // Additional decoding required for RV32
|
|||
|
|||
uint8_t bs = insn.bs(); |
|||
|
|||
uint8_t t0 = RS2 >> (8*bs); |
|||
uint8_t x = AES_ENC_SBOX[t0]; |
|||
uint32_t u = x; |
|||
|
|||
u = (u << (8*bs)) | (u >> (32-8*bs)); |
|||
|
|||
uint64_t rd = insn.rs1(); // RD sourced from RS1 field.
|
|||
WRITE_REG(rd, u ^ RS1); |
|||
|
|||
} else { |
|||
// Execute the RV64 aes64es instruction
|
|||
|
|||
require(insn.bs() == 0); |
|||
require_rv64; |
|||
require_extension('K'); |
|||
|
|||
uint64_t temp = AES_SHIFROWS_LO(RS1,RS2); |
|||
|
|||
temp = ( |
|||
((uint64_t)AES_ENC_SBOX[(temp >> 0) & 0xFF] << 0) | |
|||
((uint64_t)AES_ENC_SBOX[(temp >> 8) & 0xFF] << 8) | |
|||
((uint64_t)AES_ENC_SBOX[(temp >> 16) & 0xFF] << 16) | |
|||
((uint64_t)AES_ENC_SBOX[(temp >> 24) & 0xFF] << 24) | |
|||
((uint64_t)AES_ENC_SBOX[(temp >> 32) & 0xFF] << 32) | |
|||
((uint64_t)AES_ENC_SBOX[(temp >> 40) & 0xFF] << 40) | |
|||
((uint64_t)AES_ENC_SBOX[(temp >> 48) & 0xFF] << 48) | |
|||
((uint64_t)AES_ENC_SBOX[(temp >> 56) & 0xFF] << 56) |
|||
); |
|||
|
|||
WRITE_RD(temp); |
|||
|
|||
} |
|||
@ -0,0 +1,61 @@ |
|||
|
|||
#include "aes_common.h" |
|||
|
|||
// The encodings for the RV32 and RV64 AES instructions overlap, as they
|
|||
// are mutually exclusive. They have rather different functionality.
|
|||
|
|||
if(xlen == 32) { |
|||
// Execute the RV32 aes32esmi instruction
|
|||
|
|||
require_rv32; |
|||
require_extension('K'); |
|||
require(RD == 0); // Additional decoding required for RV32
|
|||
|
|||
uint8_t bs = insn.bs(); |
|||
|
|||
uint8_t t0 = RS2 >> (8*bs); |
|||
uint8_t x = AES_ENC_SBOX[t0]; |
|||
uint32_t u ; |
|||
|
|||
u = (AES_GFMUL(x,3) << 24) | |
|||
( x << 16) | |
|||
( x << 8) | |
|||
(AES_GFMUL(x,2) << 0) ; |
|||
|
|||
u = (u << (8*bs)) | (u >> (32-8*bs)); |
|||
|
|||
uint64_t rd = insn.rs1(); // RD sourced from RS1 field.
|
|||
WRITE_REG(rd, u ^ RS1); |
|||
|
|||
} else { |
|||
// Execute the RV64 aes64esm instruction
|
|||
|
|||
require(insn.bs() == 0); |
|||
require_rv64; |
|||
require_extension('K'); |
|||
|
|||
uint64_t temp = AES_SHIFROWS_LO(RS1,RS2); |
|||
|
|||
temp = ( |
|||
((uint64_t)AES_ENC_SBOX[(temp >> 0) & 0xFF] << 0) | |
|||
((uint64_t)AES_ENC_SBOX[(temp >> 8) & 0xFF] << 8) | |
|||
((uint64_t)AES_ENC_SBOX[(temp >> 16) & 0xFF] << 16) | |
|||
((uint64_t)AES_ENC_SBOX[(temp >> 24) & 0xFF] << 24) | |
|||
((uint64_t)AES_ENC_SBOX[(temp >> 32) & 0xFF] << 32) | |
|||
((uint64_t)AES_ENC_SBOX[(temp >> 40) & 0xFF] << 40) | |
|||
((uint64_t)AES_ENC_SBOX[(temp >> 48) & 0xFF] << 48) | |
|||
((uint64_t)AES_ENC_SBOX[(temp >> 56) & 0xFF] << 56) |
|||
); |
|||
|
|||
uint32_t col_0 = temp & 0xFFFFFFFF; |
|||
uint32_t col_1 = temp >> 32 ; |
|||
|
|||
col_0 = AES_MIXCOLUMN(col_0); |
|||
col_1 = AES_MIXCOLUMN(col_1); |
|||
|
|||
uint64_t result= ((uint64_t)col_1 << 32) | col_0; |
|||
|
|||
WRITE_RD(result); |
|||
|
|||
} |
|||
|
|||
@ -0,0 +1,13 @@ |
|||
|
|||
require_extension('K'); |
|||
|
|||
#define ROR32(a,amt) ((a << (-amt & (32-1))) | (a >> (amt & (32-1)))) |
|||
|
|||
uint32_t a = RS1; |
|||
|
|||
WRITE_RD( |
|||
ROR32(a, 7) ^ ROR32(a,18) ^ (a >> 3) |
|||
); |
|||
|
|||
#undef ROR32 |
|||
|
|||
@ -0,0 +1,13 @@ |
|||
|
|||
require_extension('K'); |
|||
|
|||
#define ROR32(a,amt) ((a << (-amt & (32-1))) | (a >> (amt & (32-1)))) |
|||
|
|||
uint32_t a = RS1; |
|||
|
|||
WRITE_RD( |
|||
ROR32(a, 17) ^ ROR32(a,19) ^ (a >> 10) |
|||
); |
|||
|
|||
#undef ROR32 |
|||
|
|||
@ -0,0 +1,13 @@ |
|||
|
|||
require_extension('K'); |
|||
|
|||
#define ROR32(a,amt) ((a << (-amt & (32-1))) | (a >> (amt & (32-1)))) |
|||
|
|||
uint32_t a = RS1; |
|||
|
|||
WRITE_RD( |
|||
ROR32(a, 2) ^ ROR32(a,13) ^ ROR32(a, 22) |
|||
); |
|||
|
|||
#undef ROR32 |
|||
|
|||
@ -0,0 +1,13 @@ |
|||
|
|||
require_extension('K'); |
|||
|
|||
#define ROR32(a,amt) ((a << (-amt & (32-1))) | (a >> (amt & (32-1)))) |
|||
|
|||
uint32_t a = RS1; |
|||
|
|||
WRITE_RD( |
|||
ROR32(a, 6) ^ ROR32(a,11) ^ ROR32(a, 25) |
|||
); |
|||
|
|||
#undef ROR32 |
|||
|
|||
@ -0,0 +1,13 @@ |
|||
require_rv64; |
|||
require_extension('K'); |
|||
|
|||
#define ROR64(a,amt) ((a << (-amt & (64-1))) | (a >> (amt & (64-1)))) |
|||
|
|||
uint64_t a = RS1; |
|||
|
|||
WRITE_RD( |
|||
ROR64(a, 1) ^ ROR64(a, 8) ^ (a >> 7) |
|||
); |
|||
|
|||
#undef ROR64 |
|||
|
|||
@ -0,0 +1,9 @@ |
|||
|
|||
require_rv32; |
|||
require_extension('K'); |
|||
|
|||
uint32_t result = |
|||
((uint32_t)RS1 >> 1) ^ ((uint32_t)RS1 >> 7) ^ ((uint32_t)RS1 >> 8) ^ |
|||
((uint32_t)RS2 << 31) ^ ((uint32_t)RS2 << 24); |
|||
|
|||
WRITE_RD(zext_xlen(result)); |
|||
@ -0,0 +1,9 @@ |
|||
|
|||
require_rv32; |
|||
require_extension('K'); |
|||
|
|||
uint32_t result = |
|||
((uint32_t)RS1 >> 1) ^ ((uint32_t)RS1 >> 7) ^ ((uint32_t)RS1 >> 8) ^ |
|||
((uint32_t)RS2 << 31) ^ ((uint32_t)RS2 << 25) ^ ((uint32_t)RS2 << 24); |
|||
|
|||
WRITE_RD(zext_xlen(result)); |
|||
@ -0,0 +1,13 @@ |
|||
require_rv64; |
|||
require_extension('K'); |
|||
|
|||
#define ROR64(a,amt) ((a << (-amt & (64-1))) | (a >> (amt & (64-1)))) |
|||
|
|||
uint64_t a = RS1; |
|||
|
|||
WRITE_RD( |
|||
ROR64(a, 19) ^ ROR64(a,61) ^ (a >> 6) |
|||
); |
|||
|
|||
#undef ROR64 |
|||
|
|||
@ -0,0 +1,9 @@ |
|||
|
|||
require_rv32; |
|||
require_extension('K'); |
|||
|
|||
uint32_t result = |
|||
((uint32_t)RS1 << 3) ^ ((uint32_t)RS1 >> 6) ^ ((uint32_t)RS1 >> 19) ^ |
|||
((uint32_t)RS2 >> 29) ^ ((uint32_t)RS2 << 13); |
|||
|
|||
WRITE_RD(zext_xlen(result)); |
|||
@ -0,0 +1,9 @@ |
|||
|
|||
require_rv32; |
|||
require_extension('K'); |
|||
|
|||
uint32_t result = |
|||
((uint32_t)RS1 << 3) ^ ((uint32_t)RS1 >> 6) ^ ((uint32_t)RS1 >> 19) ^ |
|||
((uint32_t)RS2 >> 29) ^ ((uint32_t)RS2 << 26) ^ ((uint32_t)RS2 << 13); |
|||
|
|||
WRITE_RD(zext_xlen(result)); |
|||
@ -0,0 +1,13 @@ |
|||
require_rv64; |
|||
require_extension('K'); |
|||
|
|||
#define ROR64(a,amt) ((a << (-amt & (64-1))) | (a >> (amt & (64-1)))) |
|||
|
|||
uint64_t a = RS1; |
|||
|
|||
WRITE_RD( |
|||
ROR64(a, 28) ^ ROR64(a,34) ^ ROR64(a,39) |
|||
); |
|||
|
|||
#undef ROR64 |
|||
|
|||
@ -0,0 +1,9 @@ |
|||
|
|||
require_rv32; |
|||
require_extension('K'); |
|||
|
|||
uint32_t result = |
|||
((uint32_t)RS1 << 25) ^ ((uint32_t)RS1 << 30) ^ ((uint32_t)RS1 >> 28) ^ |
|||
((uint32_t)RS2 >> 7) ^ ((uint32_t)RS2 >> 2) ^ ((uint32_t)RS2 << 4); |
|||
|
|||
WRITE_RD(zext_xlen(result)); |
|||
@ -0,0 +1,13 @@ |
|||
require_rv64; |
|||
require_extension('K'); |
|||
|
|||
#define ROR64(a,amt) ((a << (-amt & (64-1))) | (a >> (amt & (64-1)))) |
|||
|
|||
uint64_t a = RS1; |
|||
|
|||
WRITE_RD( |
|||
ROR64(a, 14) ^ ROR64(a, 18) ^ ROR64(a, 41) |
|||
); |
|||
|
|||
#undef ROR64 |
|||
|
|||
@ -0,0 +1,9 @@ |
|||
|
|||
require_rv32; |
|||
require_extension('K'); |
|||
|
|||
uint32_t result = |
|||
((uint32_t)RS1 << 23) ^ ((uint32_t)RS1 >> 14) ^ ((uint32_t)RS1 >> 18) ^ |
|||
((uint32_t)RS2 >> 9) ^ ((uint32_t)RS2 << 18) ^ ((uint32_t)RS2 << 14); |
|||
|
|||
WRITE_RD(zext_xlen(result)); |
|||
@ -0,0 +1,14 @@ |
|||
|
|||
require_extension('K'); |
|||
|
|||
#define ROL32(a,amt) ((a >> (-amt & (32-1))) | (a << (amt & (32-1)))) |
|||
|
|||
uint32_t src = RS1; |
|||
uint32_t result = src ^ ROL32(src, 9) ^ ROL32(src, 17); |
|||
|
|||
WRITE_RD( |
|||
zext_xlen(result) |
|||
); |
|||
|
|||
#undef ROL32 |
|||
|
|||
@ -0,0 +1,14 @@ |
|||
|
|||
require_extension('K'); |
|||
|
|||
#define ROL32(a,amt) ((a >> (-amt & (32-1))) | (a << (amt & (32-1)))) |
|||
|
|||
uint32_t src = RS1; |
|||
uint32_t result = src ^ ROL32(src, 15) ^ ROL32(src, 23); |
|||
|
|||
WRITE_RD( |
|||
zext_xlen(result) |
|||
); |
|||
|
|||
#undef ROL32 |
|||
|
|||
@ -0,0 +1,27 @@ |
|||
|
|||
// SM4 forward SBox. SM4 has no inverse sbox.
|
|||
static const uint8_t sm4_sbox[256] = { |
|||
0xD6, 0x90, 0xE9, 0xFE, 0xCC, 0xE1, 0x3D, 0xB7, 0x16, 0xB6, 0x14, 0xC2, |
|||
0x28, 0xFB, 0x2C, 0x05, 0x2B, 0x67, 0x9A, 0x76, 0x2A, 0xBE, 0x04, 0xC3, |
|||
0xAA, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99, 0x9C, 0x42, 0x50, 0xF4, |
|||
0x91, 0xEF, 0x98, 0x7A, 0x33, 0x54, 0x0B, 0x43, 0xED, 0xCF, 0xAC, 0x62, |
|||
0xE4, 0xB3, 0x1C, 0xA9, 0xC9, 0x08, 0xE8, 0x95, 0x80, 0xDF, 0x94, 0xFA, |
|||
0x75, 0x8F, 0x3F, 0xA6, 0x47, 0x07, 0xA7, 0xFC, 0xF3, 0x73, 0x17, 0xBA, |
|||
0x83, 0x59, 0x3C, 0x19, 0xE6, 0x85, 0x4F, 0xA8, 0x68, 0x6B, 0x81, 0xB2, |
|||
0x71, 0x64, 0xDA, 0x8B, 0xF8, 0xEB, 0x0F, 0x4B, 0x70, 0x56, 0x9D, 0x35, |
|||
0x1E, 0x24, 0x0E, 0x5E, 0x63, 0x58, 0xD1, 0xA2, 0x25, 0x22, 0x7C, 0x3B, |
|||
0x01, 0x21, 0x78, 0x87, 0xD4, 0x00, 0x46, 0x57, 0x9F, 0xD3, 0x27, 0x52, |
|||
0x4C, 0x36, 0x02, 0xE7, 0xA0, 0xC4, 0xC8, 0x9E, 0xEA, 0xBF, 0x8A, 0xD2, |
|||
0x40, 0xC7, 0x38, 0xB5, 0xA3, 0xF7, 0xF2, 0xCE, 0xF9, 0x61, 0x15, 0xA1, |
|||
0xE0, 0xAE, 0x5D, 0xA4, 0x9B, 0x34, 0x1A, 0x55, 0xAD, 0x93, 0x32, 0x30, |
|||
0xF5, 0x8C, 0xB1, 0xE3, 0x1D, 0xF6, 0xE2, 0x2E, 0x82, 0x66, 0xCA, 0x60, |
|||
0xC0, 0x29, 0x23, 0xAB, 0x0D, 0x53, 0x4E, 0x6F, 0xD5, 0xDB, 0x37, 0x45, |
|||
0xDE, 0xFD, 0x8E, 0x2F, 0x03, 0xFF, 0x6A, 0x72, 0x6D, 0x6C, 0x5B, 0x51, |
|||
0x8D, 0x1B, 0xAF, 0x92, 0xBB, 0xDD, 0xBC, 0x7F, 0x11, 0xD9, 0x5C, 0x41, |
|||
0x1F, 0x10, 0x5A, 0xD8, 0x0A, 0xC1, 0x31, 0x88, 0xA5, 0xCD, 0x7B, 0xBD, |
|||
0x2D, 0x74, 0xD0, 0x12, 0xB8, 0xE5, 0xB4, 0xB0, 0x89, 0x69, 0x97, 0x4A, |
|||
0x0C, 0x96, 0x77, 0x7E, 0x65, 0xB9, 0xF1, 0x09, 0xC5, 0x6E, 0xC6, 0x84, |
|||
0x18, 0xF0, 0x7D, 0xEC, 0x3A, 0xDC, 0x4D, 0x20, 0x79, 0xEE, 0x5F, 0x3E, |
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0xD7, 0xCB, 0x39, 0x48 |
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}; |
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|
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@ -0,0 +1,23 @@ |
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|
|||
require_extension('K'); |
|||
|
|||
#include "sm4_common.h" |
|||
|
|||
uint8_t bs = insn.bs(); |
|||
|
|||
uint32_t sb_in = (RS2 >> (8*bs)) & 0xFF; |
|||
uint32_t sb_out = (uint32_t)sm4_sbox[sb_in]; |
|||
|
|||
uint32_t linear = sb_out ^ (sb_out << 8) ^ |
|||
(sb_out << 2) ^ |
|||
(sb_out << 18) ^ |
|||
((sb_out & 0x3f) << 26) ^ |
|||
((sb_out & 0xC0) << 10) ; |
|||
|
|||
uint32_t rotl = (linear << (8*bs)) | (linear >> (32-8*bs)); |
|||
|
|||
uint32_t result = rotl ^ RS1; |
|||
uint64_t rd = insn.rs1(); // RD sourced from RS1 field.
|
|||
|
|||
WRITE_REG(rd, zext_xlen(result)); |
|||
|
|||
@ -0,0 +1,21 @@ |
|||
|
|||
require_extension('K'); |
|||
|
|||
#include "sm4_common.h" |
|||
|
|||
uint8_t bs = insn.bs(); |
|||
|
|||
uint32_t sb_in = (RS2 >> (8*bs)) & 0xFF; |
|||
uint32_t sb_out = sm4_sbox[sb_in]; |
|||
|
|||
uint32_t x = sb_out ^ |
|||
((sb_out & 0x07) << 29) ^ ((sb_out & 0xFE) << 7) ^ |
|||
((sb_out & 0x01) << 23) ^ ((sb_out & 0xF8) << 13) ; |
|||
|
|||
uint32_t rotl = (x << (8*bs)) | (x >> (32-8*bs)); |
|||
|
|||
uint32_t result = rotl ^ RS1; |
|||
uint64_t rd = insn.rs1(); // RD sourced from RS1 field.
|
|||
|
|||
WRITE_REG(rd, zext_xlen(result)); |
|||
|
|||
Loading…
Reference in new issue