[xcc,sim,opcodes] added more RVC instructions

riscv/decode.h

@@ -210,21 +210,27 @@ private:
 
 #define INSN_IS_RVC(x) (((x) & 0x3) < 0x3)
 
-#define CRD do_writeback(XPR, (insn.bits >> 5) & 0x1f)
+#define CRD_REGNUM ((insn.bits >> 5) & 0x1f)
+#define CRD do_writeback(XPR, CRD_REGNUM)
 #define CRS1 XPR[(insn.bits >> 10) & 0x1f]
 #define CRS2 XPR[(insn.bits >> 5) & 0x1f]
 #define CIMM6 ((int32_t)((insn.bits >> 10) & 0x3f) << 26 >> 26)
-#define CIMM5 ((int32_t)((insn.bits >> 5) & 0x1f) << 27 >> 27)
+#define CIMM5U ((insn.bits >> 5) & 0x1f)
+#define CIMM5 ((int32_t)CIMM5U << 27 >> 27)
 #define CIMM10 ((int32_t)((insn.bits >> 5) & 0x3ff) << 22 >> 22)
 #define CBRANCH_TARGET (pc + (CIMM5 << BRANCH_ALIGN_BITS))
 #define CJUMP_TARGET (pc + (CIMM10 << JUMP_ALIGN_BITS))
 
 static const int rvc_rs1_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 };
 #define rvc_rd_regmap rvc_rs1_regmap
+#define rvc_rs2b_regmap rvc_rs1_regmap
 static const int rvc_rs2_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 0 };
-#define CRDS do_writeback(XPR, rvc_rd_regmap[(insn.bits >> 13) & 0x7])
+#define CRDS XPR[rvc_rd_regmap[(insn.bits >> 13) & 0x7]]
+#define FCRDS FPR[rvc_rd_regmap[(insn.bits >> 13) & 0x7]]
 #define CRS1S XPR[rvc_rs1_regmap[(insn.bits >> 10) & 0x7]]
 #define CRS2S XPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
+#define CRS2BS XPR[rvc_rs2b_regmap[(insn.bits >> 5) & 0x7]]
+#define FCRS2S FPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
 
 // vector stuff
 #define VL vl

riscv/insns/c_add.h

@@ -0,0 +1,2 @@
+require_rvc;
+CRD = CRS1 + CRS2;

riscv/insns/c_add3.h

@@ -0,0 +1,2 @@
+require_rvc;
+CRDS = CRS1S + CRS2BS;

riscv/insns/c_addi.h

@@ -1,2 +1,10 @@
 require_rvc;
-CRD = sext_xprlen(CRS2 + CIMM6);
+if(CRD_REGNUM == 0)
+{
+  reg_t temp = npc;
+  npc = CRS1;
+  if(CIMM6 & 0x20)
+    RA = temp;
+}
+else
+  CRD = sext_xprlen(CRS2 + CIMM6);

riscv/insns/c_and3.h

@@ -0,0 +1,2 @@
+require_rvc;
+CRDS = CRS1S & CRS2BS;

riscv/insns/c_fld.h

@@ -0,0 +1,3 @@
+require_rvc;
+require_fp;
+FCRDS = mmu.load_int64(CRS1S+CIMM5*8);

riscv/insns/c_flw.h

@@ -0,0 +1,3 @@
+require_rvc;
+require_fp;
+FCRDS = mmu.load_int32(CRS1S+CIMM5*4);

riscv/insns/c_fsd.h

@@ -0,0 +1,3 @@
+require_rvc;
+require_fp;
+mmu.store_uint64(CRS1S+CIMM5*8, FCRS2S);

riscv/insns/c_fsw.h

@@ -0,0 +1,3 @@
+require_rvc;
+require_fp;
+mmu.store_uint32(CRS1S+CIMM5*4, FCRS2S);

riscv/insns/c_ld0.h

@@ -0,0 +1,3 @@
+require_rvc;
+require_xpr64;
+CRD = mmu.load_int64(CRS1);

riscv/insns/c_lw0.h

@@ -0,0 +1,2 @@
+require_rvc;
+CRD = mmu.load_int32(CRS1);

riscv/insns/c_or3.h

@@ -0,0 +1,2 @@
+require_rvc;
+CRDS = CRS1S | CRS2BS;

riscv/insns/c_slli.h

@@ -0,0 +1,5 @@
+require_rvc;
+if(xpr64)
+  CRDS = CRDS << CIMM5U;
+else
+  CRDS = sext32(CRDS << CIMM5U);

riscv/insns/c_slli32.h

@@ -0,0 +1,3 @@
+require_rvc;
+require_xpr64;
+CRDS = CRDS << (32+CIMM5U);

riscv/insns/c_slliw.h

@@ -0,0 +1,3 @@
+require_rvc;
+require_xpr64;
+CRDS = sext32(CRDS << CIMM5U);

riscv/insns/c_srai.h

@@ -0,0 +1,5 @@
+require_rvc;
+if(xpr64)
+  CRDS = sreg_t(CRDS) >> CIMM5U;
+else
+  CRDS = sext32(int32_t(CRDS) >> CIMM5U);

riscv/insns/c_srai32.h

@@ -0,0 +1,3 @@
+require_rvc;
+require_xpr64;
+CRDS = sreg_t(CRDS) >> (32+CIMM5U);

riscv/insns/c_srli.h

@@ -0,0 +1,5 @@
+require_rvc;
+if(xpr64)
+  CRDS = CRDS >> CIMM5U;
+else
+  CRDS = sext32(uint32_t(CRDS) >> CIMM5U);

riscv/insns/c_srli32.h

@@ -0,0 +1,3 @@
+require_rvc;
+require_xpr64;
+CRDS = CRDS >> (32+CIMM5U);

riscv/insns/c_sub.h

@@ -0,0 +1,2 @@
+require_rvc;
+CRD = CRS1 - CRS2;

riscv/insns/c_sub3.h

@@ -0,0 +1,2 @@
+require_rvc;
+CRDS = CRS1S - CRS2BS;