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riscv-isa-sim
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Renumber uarch CSRs into custom CSR space

mvp
Andrew Waterman 13 years ago
parent
6c99f30d78
commit
d47f8ca5b6
1 changed files with 16 additions and 16 deletions
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  1. 32
      riscv/encoding.h

32
riscv/encoding.h
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@ -433,22 +433,22 @@
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
#define CSR_INSTRET 0xc02
#define CSR_UARCH0 0xc10
#define CSR_UARCH1 0xc11
#define CSR_UARCH2 0xc12
#define CSR_UARCH3 0xc13
#define CSR_UARCH4 0xc14
#define CSR_UARCH5 0xc15
#define CSR_UARCH6 0xc16
#define CSR_UARCH7 0xc17
#define CSR_UARCH8 0xc18
#define CSR_UARCH9 0xc19
#define CSR_UARCH10 0xc1a
#define CSR_UARCH11 0xc1b
#define CSR_UARCH12 0xc1c
#define CSR_UARCH13 0xc1d
#define CSR_UARCH14 0xc1e
#define CSR_UARCH15 0xc1f
#define CSR_UARCH0 0xcc0
#define CSR_UARCH1 0xcc1
#define CSR_UARCH2 0xcc2
#define CSR_UARCH3 0xcc3
#define CSR_UARCH4 0xcc4
#define CSR_UARCH5 0xcc5
#define CSR_UARCH6 0xcc6
#define CSR_UARCH7 0xcc7
#define CSR_UARCH8 0xcc8
#define CSR_UARCH9 0xcc9
#define CSR_UARCH10 0xcca
#define CSR_UARCH11 0xccb
#define CSR_UARCH12 0xccc
#define CSR_UARCH13 0xccd
#define CSR_UARCH14 0xcce
#define CSR_UARCH15 0xccf
#define CAUSE_MISALIGNED_FETCH 0x0
#define CAUSE_FAULT_FETCH 0x1
#define CAUSE_ILLEGAL_INSTRUCTION 0x2

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