riscv
/
riscv-isa-sim
mirror of https://github.com/riscv-software-src/riscv-isa-sim.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
Browse Source

Merge branch 'viktoryou-master'

pull/1453/head
Andrew Waterman 3 years ago
parent
5854ab5218 3c8320ecd7
commit
d2d9d995a9
1 changed files with 3 additions and 3 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Unified View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 6
      riscv/insns/cbo_inval.h

6
riscv/insns/cbo_inval.h
View File

@ -1,9 +1,9 @@
require_extension(EXT_ZICBOM); require_extension(EXT_ZICBOM);
DECLARE_XENVCFG_VARS(CBIE); DECLARE_XENVCFG_VARS(CBIE);
require_envcfg(CBIE); require_envcfg(CBIE);
if (((STATE.prv != PRV_M) && (mCBIE == 1)) || if ((STATE.prv != PRV_M && mCBIE) ||
((!STATE.v && (STATE.prv == PRV_U)) && (sCBIE = 1)) || (!STATE.v && STATE.prv == PRV_U && sCBIE) ||
(STATE.v && ((hCBIE == 1) || ((STATE.prv == PRV_U) && (sCBIE== 0))))) (STATE.v && (hCBIE || (STATE.prv == PRV_U && sCBIE))))
MMU.clean_inval(RS1, true, true); MMU.clean_inval(RS1, true, true);
else else
MMU.clean_inval(RS1, false, true); MMU.clean_inval(RS1, false, true);

Write Preview
Loading…
Cancel
Save