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zve: some MUL operaiton are unavailable to zve64

Based on section 18.2 in spec

"All Zve* extensions support all vector integer instructions (Section
Vector Integer Arithmetic Instructions), except that the vmulh integer
multiply variants that return the high word of the product (vmulh.vv,
        vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx) are not
included for EEW=64 in Zve64*."

"All Zve* extensions support all vector fixed-point arithmetic
instructions (Vector Fixed-Point Arithmetic Instructions), except that
vsmul.vv and vsmul.vx are not included in EEW=64 in Zve64*"

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
pull/2153/head
Chih-Min Chao 8 months ago
parent
commit
d1e34d021f
  1. 2
      riscv/insns/vmulh_vv.h
  2. 2
      riscv/insns/vmulh_vx.h
  3. 2
      riscv/insns/vmulhsu_vv.h
  4. 2
      riscv/insns/vmulhsu_vx.h
  5. 2
      riscv/insns/vmulhu_vv.h
  6. 2
      riscv/insns/vmulhu_vx.h
  7. 2
      riscv/insns/vsmul_vv.h
  8. 2
      riscv/insns/vsmul_vx.h

2
riscv/insns/vmulh_vv.h

@ -1,4 +1,6 @@
// vmulh vd, vs2, vs1 // vmulh vd, vs2, vs1
require(p->extension_enabled('V') || P.VU.vsew < e64);
VI_VV_LOOP VI_VV_LOOP
({ ({
vd = ((int128_t)vs2 * vs1) >> sew; vd = ((int128_t)vs2 * vs1) >> sew;

2
riscv/insns/vmulh_vx.h

@ -1,4 +1,6 @@
// vmulh vd, vs2, rs1 // vmulh vd, vs2, rs1
require(p->extension_enabled('V') || P.VU.vsew < e64);
VI_VX_LOOP VI_VX_LOOP
({ ({
vd = ((int128_t)vs2 * rs1) >> sew; vd = ((int128_t)vs2 * rs1) >> sew;

2
riscv/insns/vmulhsu_vv.h

@ -1,4 +1,6 @@
// vmulhsu.vv vd, vs2, vs1 // vmulhsu.vv vd, vs2, vs1
require(p->extension_enabled('V') || P.VU.vsew < e64);
VI_VV_SU_LOOP({ VI_VV_SU_LOOP({
vd = ((int128_t)vs2 * (uint128_t)vs1) >> sew; vd = ((int128_t)vs2 * (uint128_t)vs1) >> sew;
}) })

2
riscv/insns/vmulhsu_vx.h

@ -1,4 +1,6 @@
// vmulhsu.vx vd, vs2, rs1 // vmulhsu.vx vd, vs2, rs1
require(p->extension_enabled('V') || P.VU.vsew < e64);
VI_VX_SU_LOOP({ VI_VX_SU_LOOP({
vd = ((int128_t)vs2 * (uint128_t)rs1) >> sew; vd = ((int128_t)vs2 * (uint128_t)rs1) >> sew;
}) })

2
riscv/insns/vmulhu_vv.h

@ -1,4 +1,6 @@
// vmulhu vd, vs2, vs1 // vmulhu vd, vs2, vs1
require(p->extension_enabled('V') || P.VU.vsew < e64);
VI_VV_ULOOP VI_VV_ULOOP
({ ({
vd = ((uint128_t)vs2 * vs1) >> sew; vd = ((uint128_t)vs2 * vs1) >> sew;

2
riscv/insns/vmulhu_vx.h

@ -1,4 +1,6 @@
// vmulhu vd ,vs2, rs1 // vmulhu vd ,vs2, rs1
require(p->extension_enabled('V') || P.VU.vsew < e64);
VI_VX_ULOOP VI_VX_ULOOP
({ ({
vd = ((uint128_t)vs2 * rs1) >> sew; vd = ((uint128_t)vs2 * rs1) >> sew;

2
riscv/insns/vsmul_vv.h

@ -1,4 +1,6 @@
// vsmul.vv vd, vs2, vs1 // vsmul.vv vd, vs2, vs1
require(p->extension_enabled('V') || P.VU.vsew < e64);
VI_VV_LOOP VI_VV_LOOP
({ ({
VRM xrm = P.VU.get_vround_mode(); VRM xrm = P.VU.get_vround_mode();

2
riscv/insns/vsmul_vx.h

@ -1,4 +1,6 @@
// vsmul.vx vd, vs2, rs1 // vsmul.vx vd, vs2, rs1
require(p->extension_enabled('V') || P.VU.vsew < e64);
VI_VX_LOOP VI_VX_LOOP
({ ({
VRM xrm = P.VU.get_vround_mode(); VRM xrm = P.VU.get_vround_mode();

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