From d1e34d021fdbb454e9744dd8602d80347b076af6 Mon Sep 17 00:00:00 2001
From: Chih-Min Chao <chihmin.chao@sifive.com>
Date: Tue, 30 Sep 2025 23:27:20 -0700
Subject: [PATCH] zve: some MUL operaiton are unavailable to zve64

Based on section 18.2 in spec

"All Zve* extensions support all vector integer instructions (Section
Vector Integer Arithmetic Instructions), except that the vmulh integer
multiply variants that return the high word of the product (vmulh.vv,
        vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx) are not
included for EEW=64 in Zve64*."

"All Zve* extensions support all vector fixed-point arithmetic
instructions (Vector Fixed-Point Arithmetic Instructions), except that
vsmul.vv and vsmul.vx are not included in EEW=64 in Zve64*"

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
---
 riscv/insns/vmulh_vv.h   | 2 ++
 riscv/insns/vmulh_vx.h   | 2 ++
 riscv/insns/vmulhsu_vv.h | 2 ++
 riscv/insns/vmulhsu_vx.h | 2 ++
 riscv/insns/vmulhu_vv.h  | 2 ++
 riscv/insns/vmulhu_vx.h  | 2 ++
 riscv/insns/vsmul_vv.h   | 2 ++
 riscv/insns/vsmul_vx.h   | 2 ++
 8 files changed, 16 insertions(+)

diff --git a/riscv/insns/vmulh_vv.h b/riscv/insns/vmulh_vv.h
index e861a339..273d3e86 100644
--- a/riscv/insns/vmulh_vv.h
+++ b/riscv/insns/vmulh_vv.h
@@ -1,4 +1,6 @@
 // vmulh vd, vs2, vs1
+require(p->extension_enabled('V') || P.VU.vsew < e64);
+
 VI_VV_LOOP
 ({
   vd = ((int128_t)vs2 * vs1) >> sew;
diff --git a/riscv/insns/vmulh_vx.h b/riscv/insns/vmulh_vx.h
index b6b55036..aaf591c1 100644
--- a/riscv/insns/vmulh_vx.h
+++ b/riscv/insns/vmulh_vx.h
@@ -1,4 +1,6 @@
 // vmulh vd, vs2, rs1
+require(p->extension_enabled('V') || P.VU.vsew < e64);
+
 VI_VX_LOOP
 ({
   vd = ((int128_t)vs2 * rs1) >> sew;
diff --git a/riscv/insns/vmulhsu_vv.h b/riscv/insns/vmulhsu_vv.h
index e1c0ba60..3903d524 100644
--- a/riscv/insns/vmulhsu_vv.h
+++ b/riscv/insns/vmulhsu_vv.h
@@ -1,4 +1,6 @@
 // vmulhsu.vv vd, vs2, vs1
+require(p->extension_enabled('V') || P.VU.vsew < e64);
+
 VI_VV_SU_LOOP({
   vd = ((int128_t)vs2 * (uint128_t)vs1) >> sew;
 })
diff --git a/riscv/insns/vmulhsu_vx.h b/riscv/insns/vmulhsu_vx.h
index 4619ea89..b8210bc3 100644
--- a/riscv/insns/vmulhsu_vx.h
+++ b/riscv/insns/vmulhsu_vx.h
@@ -1,4 +1,6 @@
 // vmulhsu.vx vd, vs2, rs1
+require(p->extension_enabled('V') || P.VU.vsew < e64);
+
 VI_VX_SU_LOOP({
   vd = ((int128_t)vs2 * (uint128_t)rs1) >> sew;
 })
diff --git a/riscv/insns/vmulhu_vv.h b/riscv/insns/vmulhu_vv.h
index 0ff488c3..5e44aec9 100644
--- a/riscv/insns/vmulhu_vv.h
+++ b/riscv/insns/vmulhu_vv.h
@@ -1,4 +1,6 @@
 // vmulhu vd, vs2, vs1
+require(p->extension_enabled('V') || P.VU.vsew < e64);
+
 VI_VV_ULOOP
 ({
   vd = ((uint128_t)vs2 * vs1) >> sew;
diff --git a/riscv/insns/vmulhu_vx.h b/riscv/insns/vmulhu_vx.h
index 672ad32d..35e6ed69 100644
--- a/riscv/insns/vmulhu_vx.h
+++ b/riscv/insns/vmulhu_vx.h
@@ -1,4 +1,6 @@
 // vmulhu vd ,vs2, rs1
+require(p->extension_enabled('V') || P.VU.vsew < e64);
+
 VI_VX_ULOOP
 ({
   vd = ((uint128_t)vs2 * rs1) >> sew;
diff --git a/riscv/insns/vsmul_vv.h b/riscv/insns/vsmul_vv.h
index c1d0a570..bacd7573 100644
--- a/riscv/insns/vsmul_vv.h
+++ b/riscv/insns/vsmul_vv.h
@@ -1,4 +1,6 @@
 // vsmul.vv vd, vs2, vs1
+require(p->extension_enabled('V') || P.VU.vsew < e64);
+
 VI_VV_LOOP
 ({
   VRM xrm = P.VU.get_vround_mode();
diff --git a/riscv/insns/vsmul_vx.h b/riscv/insns/vsmul_vx.h
index c2e531cb..62dfa7c4 100644
--- a/riscv/insns/vsmul_vx.h
+++ b/riscv/insns/vsmul_vx.h
@@ -1,4 +1,6 @@
 // vsmul.vx vd, vs2, rs1
+require(p->extension_enabled('V') || P.VU.vsew < e64);
+
 VI_VX_LOOP
 ({
   VRM xrm = P.VU.get_vround_mode();