diff --git a/riscv/insns/vmulh_vv.h b/riscv/insns/vmulh_vv.h
index e861a339..273d3e86 100644
--- a/riscv/insns/vmulh_vv.h
+++ b/riscv/insns/vmulh_vv.h
@@ -1,4 +1,6 @@
 // vmulh vd, vs2, vs1
+require(p->extension_enabled('V') || P.VU.vsew < e64);
+
 VI_VV_LOOP
 ({
   vd = ((int128_t)vs2 * vs1) >> sew;
diff --git a/riscv/insns/vmulh_vx.h b/riscv/insns/vmulh_vx.h
index b6b55036..aaf591c1 100644
--- a/riscv/insns/vmulh_vx.h
+++ b/riscv/insns/vmulh_vx.h
@@ -1,4 +1,6 @@
 // vmulh vd, vs2, rs1
+require(p->extension_enabled('V') || P.VU.vsew < e64);
+
 VI_VX_LOOP
 ({
   vd = ((int128_t)vs2 * rs1) >> sew;
diff --git a/riscv/insns/vmulhsu_vv.h b/riscv/insns/vmulhsu_vv.h
index e1c0ba60..3903d524 100644
--- a/riscv/insns/vmulhsu_vv.h
+++ b/riscv/insns/vmulhsu_vv.h
@@ -1,4 +1,6 @@
 // vmulhsu.vv vd, vs2, vs1
+require(p->extension_enabled('V') || P.VU.vsew < e64);
+
 VI_VV_SU_LOOP({
   vd = ((int128_t)vs2 * (uint128_t)vs1) >> sew;
 })
diff --git a/riscv/insns/vmulhsu_vx.h b/riscv/insns/vmulhsu_vx.h
index 4619ea89..b8210bc3 100644
--- a/riscv/insns/vmulhsu_vx.h
+++ b/riscv/insns/vmulhsu_vx.h
@@ -1,4 +1,6 @@
 // vmulhsu.vx vd, vs2, rs1
+require(p->extension_enabled('V') || P.VU.vsew < e64);
+
 VI_VX_SU_LOOP({
   vd = ((int128_t)vs2 * (uint128_t)rs1) >> sew;
 })
diff --git a/riscv/insns/vmulhu_vv.h b/riscv/insns/vmulhu_vv.h
index 0ff488c3..5e44aec9 100644
--- a/riscv/insns/vmulhu_vv.h
+++ b/riscv/insns/vmulhu_vv.h
@@ -1,4 +1,6 @@
 // vmulhu vd, vs2, vs1
+require(p->extension_enabled('V') || P.VU.vsew < e64);
+
 VI_VV_ULOOP
 ({
   vd = ((uint128_t)vs2 * vs1) >> sew;
diff --git a/riscv/insns/vmulhu_vx.h b/riscv/insns/vmulhu_vx.h
index 672ad32d..35e6ed69 100644
--- a/riscv/insns/vmulhu_vx.h
+++ b/riscv/insns/vmulhu_vx.h
@@ -1,4 +1,6 @@
 // vmulhu vd ,vs2, rs1
+require(p->extension_enabled('V') || P.VU.vsew < e64);
+
 VI_VX_ULOOP
 ({
   vd = ((uint128_t)vs2 * rs1) >> sew;
diff --git a/riscv/insns/vsmul_vv.h b/riscv/insns/vsmul_vv.h
index c1d0a570..bacd7573 100644
--- a/riscv/insns/vsmul_vv.h
+++ b/riscv/insns/vsmul_vv.h
@@ -1,4 +1,6 @@
 // vsmul.vv vd, vs2, vs1
+require(p->extension_enabled('V') || P.VU.vsew < e64);
+
 VI_VV_LOOP
 ({
   VRM xrm = P.VU.get_vround_mode();
diff --git a/riscv/insns/vsmul_vx.h b/riscv/insns/vsmul_vx.h
index c2e531cb..62dfa7c4 100644
--- a/riscv/insns/vsmul_vx.h
+++ b/riscv/insns/vsmul_vx.h
@@ -1,4 +1,6 @@
 // vsmul.vx vd, vs2, rs1
+require(p->extension_enabled('V') || P.VU.vsew < e64);
+
 VI_VX_LOOP
 ({
   VRM xrm = P.VU.get_vround_mode();