From d15d781737d7e9d6d70bb7987e2f38c5079dd9d5 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 13 Jan 2020 12:08:47 -0800 Subject: [PATCH] Expose sstatus.vs field --- riscv/processor.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/riscv/processor.cc b/riscv/processor.cc index 0dd0abfe..a2433d9a 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -822,6 +822,7 @@ reg_t processor_t::get_csr(int which) case CSR_MCOUNTEREN: return state.mcounteren; case CSR_SSTATUS: { reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS + | (supports_extension('V') ? SSTATUS_VS : 0) | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_UXL; reg_t sstatus = state.mstatus & mask; if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||