rvv: fp16: support conversion instrucitons

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

riscv/decode.h

@@ -1978,6 +1978,33 @@ for (reg_t i = 0; i < vlmax && P.VU.vl != 0; ++i) { \
   DEBUG_RVV_FP_VV; \
   VI_VFP_LOOP_END
 
+#define VI_VFP_CVT_SCALE(BODY16, BODY32, is_widen) \
+  if (is_widen) { \
+    VI_CHECK_DSS(false);\
+  } else { \
+    VI_CHECK_SDS(false); \
+  } \
+  require((P.VU.vsew == e16 && p->supports_extension('F')) || \
+          (P.VU.vsew == e32 && p->supports_extension('D'))); \
+  switch(P.VU.vsew) { \
+    case e16: {\
+      VI_VFP_LOOP_BASE \
+        BODY16 \
+        set_fp_exceptions; \
+      VI_VFP_LOOP_END \
+      } \
+      break; \
+    case e32: {\
+      VI_VFP_LOOP_BASE \
+        BODY32 \
+        set_fp_exceptions; \
+      VI_VFP_LOOP_END \
+      } \
+      break; \
+    default: \
+      require(0); \
+      break; \
+  }
 
 #define DEBUG_START             0x0
 #define DEBUG_END               (0x1000 - 1)

riscv/insns/vfcvt_f_x_v.h

@@ -1,7 +1,7 @@
 // vfcvt.f.x.v vd, vd2, vm
 VI_VFP_VF_LOOP
 ({
-  auto vs2_i = P.VU.elt<int32_t>(rs2_num, i);
+  auto vs2_i = P.VU.elt<int16_t>(rs2_num, i);
   vd = i32_to_f16(vs2_i);
 },
 {

riscv/insns/vfcvt_f_xu_v.h

@@ -1,7 +1,7 @@
 // vfcvt.f.xu.v vd, vd2, vm
 VI_VFP_VF_LOOP
 ({
-  auto vs2_u = P.VU.elt<uint32_t>(rs2_num, i);
+  auto vs2_u = P.VU.elt<uint16_t>(rs2_num, i);
   vd = ui32_to_f16(vs2_u);
 },
 {

riscv/insns/vfcvt_rtz_x_f_v.h

@@ -1,12 +1,10 @@
-// vfcvt.x.f.v vd, vd2, vm
+// vfcvt.rtz.x.f.v vd, vd2, vm
 VI_VFP_VF_LOOP
 ({
-  softfloat_roundingMode = softfloat_round_minMag;
-  P.VU.elt<int16_t>(rd_num, i) = f16_to_i32(vs2, STATE.frm, true);
+  P.VU.elt<int16_t>(rd_num, i) = f16_to_i16(vs2, softfloat_round_minMag, true);
 },
 {
-  softfloat_roundingMode = softfloat_round_minMag;
-  P.VU.elt<int32_t>(rd_num, i) = f32_to_i32(vs2, STATE.frm, true);
+  P.VU.elt<int32_t>(rd_num, i) = f32_to_i32(vs2, softfloat_round_minMag, true);
 },
 {
   P.VU.elt<int64_t>(rd_num, i) = f64_to_i64(vs2, softfloat_round_minMag, true);

riscv/insns/vfcvt_rtz_xu_f_v.h

@@ -1,12 +1,10 @@
-// vfcvt.xu.f.v vd, vd2, vm
+// vfcvt.rtz.xu.f.v vd, vd2, vm
 VI_VFP_VF_LOOP
 ({
-  softfloat_roundingMode = softfloat_round_minMag;
-  P.VU.elt<uint16_t>(rd_num, i) = f16_to_ui32(vs2, STATE.frm, true);
+  P.VU.elt<uint16_t>(rd_num, i) = f16_to_ui16(vs2, softfloat_round_minMag, true);
 },
 {
-  softfloat_roundingMode = softfloat_round_minMag;
-  P.VU.elt<uint32_t>(rd_num, i) = f32_to_ui32(vs2, STATE.frm, true);
+  P.VU.elt<uint32_t>(rd_num, i) = f32_to_ui32(vs2, softfloat_round_minMag, true);
 },
 {
   P.VU.elt<uint64_t>(rd_num, i) = f64_to_ui64(vs2, softfloat_round_minMag, true);

riscv/insns/vfcvt_x_f_v.h

@@ -1,7 +1,7 @@
 // vfcvt.x.f.v vd, vd2, vm
 VI_VFP_VF_LOOP
 ({
-  P.VU.elt<int32_t>(rd_num, i) = f16_to_i32(vs2, STATE.frm, true);
+  P.VU.elt<int16_t>(rd_num, i) = f16_to_i16(vs2, STATE.frm, true);
 },
 {
   P.VU.elt<int32_t>(rd_num, i) = f32_to_i32(vs2, STATE.frm, true);

riscv/insns/vfcvt_xu_f_v.h

@@ -1,7 +1,7 @@
 // vfcvt.xu.f.v vd, vd2, vm
 VI_VFP_VV_LOOP
 ({
-  P.VU.elt<uint32_t>(rd_num, i) = f16_to_ui32(vs2, STATE.frm, true);
+  P.VU.elt<uint16_t>(rd_num, i) = f16_to_ui16(vs2, STATE.frm, true);
 },
 {
   P.VU.elt<uint32_t>(rd_num, i) = f32_to_ui32(vs2, STATE.frm, true);

riscv/insns/vfncvt_f_f_w.h

@@ -1,10 +1,11 @@
 // vfncvt.f.f.v vd, vs2, vm
-VI_CHECK_SDS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+VI_VFP_CVT_SCALE
+({
+  auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
+  P.VU.elt<float16_t>(rd_num, i, true) = f32_to_f16(vs2);
+},
+{
   auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
   P.VU.elt<float32_t>(rd_num, i, true) = f64_to_f32(vs2);
-  set_fp_exceptions;
-VI_VFP_LOOP_END
+}, false)
+

riscv/insns/vfncvt_f_x_w.h

@@ -1,10 +1,10 @@
 // vfncvt.f.x.v vd, vs2, vm
-VI_CHECK_SDS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+VI_VFP_CVT_SCALE
+({
+  auto vs2 = P.VU.elt<int32_t>(rs2_num, i);
+  P.VU.elt<float16_t>(rd_num, i, true) = i32_to_f16(vs2);
+},
+{
   auto vs2 = P.VU.elt<int64_t>(rs2_num, i);
   P.VU.elt<float32_t>(rd_num, i, true) = i64_to_f32(vs2);
-  set_fp_exceptions;
-VI_VFP_LOOP_END
+}, false)

riscv/insns/vfncvt_f_xu_w.h

@@ -1,10 +1,10 @@
 // vfncvt.f.xu.v vd, vs2, vm
-VI_CHECK_SDS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+VI_VFP_CVT_SCALE
+({
+  auto vs2 = P.VU.elt<uint32_t>(rs2_num, i);
+  P.VU.elt<float16_t>(rd_num, i, true) = ui32_to_f16(vs2);
+},
+{
   auto vs2 = P.VU.elt<uint64_t>(rs2_num, i);
   P.VU.elt<float32_t>(rd_num, i, true) = ui64_to_f32(vs2);
-  set_fp_exceptions;
-VI_VFP_LOOP_END
+}, false)

riscv/insns/vfncvt_rod_f_f_w.h

@@ -1,11 +1,12 @@
-// vfncvt.f.f.v vd, vs2, vm
-VI_CHECK_SDS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+// vfncvt.rod.f.f.v vd, vs2, vm
+VI_VFP_CVT_SCALE
+({
+  softfloat_roundingMode = softfloat_round_odd;
+  auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
+  P.VU.elt<float16_t>(rd_num, i, true) = f32_to_f16(vs2);
+},
+{
   softfloat_roundingMode = softfloat_round_odd;
   auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
   P.VU.elt<float32_t>(rd_num, i, true) = f64_to_f32(vs2);
-  set_fp_exceptions;
-VI_VFP_LOOP_END
+}, false)

riscv/insns/vfncvt_rtz_x_f_w.h

@@ -1,10 +1,10 @@
-// vfncvt.x.f.v vd, vs2, vm
-VI_CHECK_SDS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+// vfncvt.rtz.x.f.w vd, vs2, vm
+VI_VFP_CVT_SCALE
+({
+  auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
+  P.VU.elt<int16_t>(rd_num, i, true) = f32_to_i16(vs2, softfloat_round_minMag, true);
+},
+{
   auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
   P.VU.elt<int32_t>(rd_num, i, true) = f64_to_i32(vs2, softfloat_round_minMag, true);
-  set_fp_exceptions;
-VI_VFP_LOOP_END
+}, false)

riscv/insns/vfncvt_rtz_xu_f_w.h

@@ -1,10 +1,10 @@
-// vfncvt.xu.f.v vd, vs2, vm
-VI_CHECK_SDS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+// vfncvt.rtz.xu.f.w vd, vs2, vm
+VI_VFP_CVT_SCALE
+({
+  auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
+  P.VU.elt<uint16_t>(rd_num, i, true) = f32_to_ui16(vs2, softfloat_round_minMag, true);
+},
+{
   auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
   P.VU.elt<uint32_t>(rd_num, i, true) = f64_to_ui32(vs2, softfloat_round_minMag, true);
-  set_fp_exceptions;
-VI_VFP_LOOP_END
+}, false)

riscv/insns/vfncvt_x_f_w.h

@@ -1,10 +1,10 @@
-// vfncvt.x.f.v vd, vs2, vm
-VI_CHECK_SDS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+// vfncvt.x.f.w vd, vs2, vm
+VI_VFP_CVT_SCALE
+({
+  auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
+  P.VU.elt<int16_t>(rd_num, i, true) = f32_to_i16(vs2, STATE.frm, true);
+},
+{
   auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
   P.VU.elt<int32_t>(rd_num, i, true) = f64_to_i32(vs2, STATE.frm, true);
-  set_fp_exceptions;
-VI_VFP_LOOP_END
+}, false)

riscv/insns/vfncvt_xu_f_w.h

@@ -1,10 +1,10 @@
-// vfncvt.xu.f.v vd, vs2, vm
-VI_CHECK_SDS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+// vfncvt.xu.f.w vd, vs2, vm
+VI_VFP_CVT_SCALE
+({
+  auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
+  P.VU.elt<uint16_t>(rd_num, i, true) = f32_to_ui16(vs2, STATE.frm, true);
+},
+{
   auto vs2 = P.VU.elt<float64_t>(rs2_num, i);
   P.VU.elt<uint32_t>(rd_num, i, true) = f64_to_ui32(vs2, STATE.frm, true);
-  set_fp_exceptions;
-VI_VFP_LOOP_END
+}, false)

riscv/insns/vfwcvt_f_f_v.h

@@ -1,10 +1,10 @@
 // vfwcvt.f.f.v vd, vs2, vm
-VI_CHECK_DSS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+VI_VFP_CVT_SCALE
+({
+  auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
+  P.VU.elt<float32_t>(rd_num, i, true) = f16_to_f32(vs2);
+},
+{
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<float64_t>(rd_num, i, true) = f32_to_f64(vs2);
-  set_fp_exceptions;
-VI_VFP_LOOP_END
+}, true)

riscv/insns/vfwcvt_f_x_v.h

@@ -1,10 +1,10 @@
 // vfwcvt.f.x.v vd, vs2, vm
-VI_CHECK_DSS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+VI_VFP_CVT_SCALE
+({
+  auto vs2 = P.VU.elt<int16_t>(rs2_num, i);
+  P.VU.elt<float32_t>(rd_num, i, true) = i32_to_f32(vs2);
+},
+{
   auto vs2 = P.VU.elt<int32_t>(rs2_num, i);
   P.VU.elt<float64_t>(rd_num, i, true) = i32_to_f64(vs2);
-  set_fp_exceptions;
-VI_VFP_LOOP_END
+}, true)

riscv/insns/vfwcvt_f_xu_v.h

@@ -1,10 +1,10 @@
 // vfwcvt.f.xu.v vd, vs2, vm
-VI_CHECK_DSS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+VI_VFP_CVT_SCALE
+({
+  auto vs2 = P.VU.elt<uint16_t>(rs2_num, i);
+  P.VU.elt<float32_t>(rd_num, i, true) = ui32_to_f32(vs2);
+},
+{
   auto vs2 = P.VU.elt<uint32_t>(rs2_num, i);
   P.VU.elt<float64_t>(rd_num, i, true) = ui32_to_f64(vs2);
-  set_fp_exceptions;
-VI_VFP_LOOP_END
+}, true)

riscv/insns/vfwcvt_rtz_x_f_v.h

@@ -1,10 +1,10 @@
-// vfwcvt.x.f.v vd, vs2, vm
-VI_CHECK_DSS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+// vfwcvt.rtz.x.f.v vd, vs2, vm
+VI_VFP_CVT_SCALE
+({
+  auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
+  P.VU.elt<int32_t>(rd_num, i, true) = f16_to_i32(vs2, softfloat_round_minMag, true);
+},
+{
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<int64_t>(rd_num, i, true) = f32_to_i64(vs2, softfloat_round_minMag, true);
-  set_fp_exceptions;
-VI_VFP_LOOP_END
+}, true)

riscv/insns/vfwcvt_rtz_xu_f_v.h

@@ -1,10 +1,10 @@
-// vfwcvt.xu.f.v vd, vs2, vm
-VI_CHECK_DSS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+// vfwcvt.rtz,xu.f.v vd, vs2, vm
+VI_VFP_CVT_SCALE
+({
+  auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
+  P.VU.elt<uint32_t>(rd_num, i, true) = f16_to_ui32(vs2, softfloat_round_minMag, true);
+},
+{
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<uint64_t>(rd_num, i, true) = f32_to_ui64(vs2, softfloat_round_minMag, true);
-  set_fp_exceptions;
-VI_VFP_LOOP_END
+}, true)

riscv/insns/vfwcvt_x_f_v.h

@@ -1,10 +1,10 @@
 // vfwcvt.x.f.v vd, vs2, vm
-VI_CHECK_DSS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+VI_VFP_CVT_SCALE
+({
+  auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
+  P.VU.elt<int32_t>(rd_num, i, true) = f16_to_i32(vs2, STATE.frm, true);
+},
+{
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<int64_t>(rd_num, i, true) = f32_to_i64(vs2, STATE.frm, true);
-  set_fp_exceptions;
-VI_VFP_LOOP_END
+}, true)

riscv/insns/vfwcvt_xu_f_v.h

@@ -1,10 +1,10 @@
 // vfwcvt.xu.f.v vd, vs2, vm
-VI_CHECK_DSS(false);
-if (P.VU.vsew == e32)
-  require(p->supports_extension('D'));
-
-VI_VFP_LOOP_BASE
+VI_VFP_CVT_SCALE
+({
+  auto vs2 = P.VU.elt<float16_t>(rs2_num, i);
+  P.VU.elt<uint32_t>(rd_num, i, true) = f16_to_ui32(vs2, STATE.frm, true);
+},
+{
   auto vs2 = P.VU.elt<float32_t>(rs2_num, i);
   P.VU.elt<uint64_t>(rd_num, i, true) = f32_to_ui64(vs2, STATE.frm, true);
-  set_fp_exceptions;
-VI_VFP_LOOP_END
+}, true)

spike_main/disasm.cc

@@ -990,10 +990,10 @@ disassembler_t::disassembler_t(int xlen)
                 match_##name##cvt_f_x_##suf, mask_##name##cvt_f_x_##suf, \
                 {&vd, &vs2, &opt, &vm})); \
     add_insn(new disasm_insn_t(#name "cvt.rtz.xu.f." #suf, \
-                match_##name##cvt_xu_f_##suf, mask_##name##cvt_xu_f_##suf, \
+                match_##name##cvt_rtz_xu_f_##suf, mask_##name##cvt_rtz_xu_f_##suf, \
                 {&vd, &vs2, &opt, &vm})); \
     add_insn(new disasm_insn_t(#name "cvt.rtz.x.f." #suf, \
-                match_##name##cvt_x_f_##suf, mask_##name##cvt_x_f_##suf, \
+                match_##name##cvt_rtz_x_f_##suf, mask_##name##cvt_rtz_x_f_##suf, \
                 {&vd, &vs2, &opt, &vm})); \
 
   //OPFVV/OPFVF