Add space between if/while/switch and '('

Add space between ')' and '{'

riscv/cachesim.cc

@@ -39,9 +39,9 @@ cache_sim_t* cache_sim_t::construct(const char* config, const char* name)
 
 void cache_sim_t::init()
 {
-  if(sets == 0 || (sets & (sets-1)))
+  if (sets == 0 || (sets & (sets-1)))
     help();
-  if(linesz < 8 || (linesz & (linesz-1)))
+  if (linesz < 8 || (linesz & (linesz-1)))
     help();
 
   idx_shift = 0;
@@ -76,7 +76,7 @@ cache_sim_t::~cache_sim_t()
 
 void cache_sim_t::print_stats()
 {
-  if(read_accesses + write_accesses == 0)
+  if (read_accesses + write_accesses == 0)
     return;
 
   float mr = 100.0f*(read_misses+write_misses)/(read_accesses+write_accesses);

riscv/debug_module.cc

@@ -215,7 +215,7 @@ bool debug_module_t::store(reg_t addr, size_t len, const uint8_t* bytes)
       }
     }
     if (dmcontrol.hartsel == id) {
-      if (0 == (debug_rom_flags[id] & (1 << DEBUG_ROM_FLAG_GO))){
+      if (0 == (debug_rom_flags[id] & (1 << DEBUG_ROM_FLAG_GO))) {
         if (dmcontrol.hartsel == id) {
           abstract_command_completed = true;
         }

riscv/decode.h

@@ -251,7 +251,7 @@ do { \
   else { \
     WRITE_FRD(value); \
   } \
-} while(0)
+} while (0)
 #define WRITE_FRD_F(value) \
 do { \
   if (p->extension_enabled(EXT_ZFINX)) \
@@ -259,7 +259,7 @@ do { \
   else { \
     WRITE_FRD(value); \
   } \
-} while(0)
+} while (0)
 #define WRITE_FRD_D(value) \
 do { \
   if (p->extension_enabled(EXT_ZFINX)) { \
@@ -272,7 +272,7 @@ do { \
   } else { \
     WRITE_FRD(value); \
   } \
-} while(0)
+} while (0)
  
 #define SHAMT (insn.i_imm() & 0x3F)
 #define BRANCH_TARGET (pc + insn.sb_imm())

riscv/entropy_source.h

@@ -49,21 +49,21 @@ public:
     // the bare minimum.
     uint32_t return_status = OPST_ES16;
 
-    if(return_status == OPST_ES16) {
+    if (return_status == OPST_ES16) {
 
       // Add some sampled entropy into the low 16 bits
       uint16_t entropy = this -> get_two_random_bytes();
       result |= entropy;
 
-    } else if(return_status == OPST_BIST) {
+    } else if (return_status == OPST_BIST) {
 
       // Do nothing.
 
-    } else if(return_status == OPST_WAIT) {
+    } else if (return_status == OPST_WAIT) {
 
       // Do nothing.
 
-    } else if(return_status == OPST_DEAD) {
+    } else if (return_status == OPST_DEAD) {
 
       // Do nothing. Stay dead.
 
@@ -94,7 +94,7 @@ public:
 
     std::ifstream fh(this -> randomness_source, std::ios::binary);
 
-    if(fh.is_open()) {
+    if (fh.is_open()) {
 
       uint16_t random_bytes;
 

riscv/insns/aes64ks1i.h

@@ -10,7 +10,7 @@ uint8_t     round_consts [10] = {
 
 uint8_t     enc_rcon          = insn.rcon() ;
 
-if(enc_rcon > 0xA) {
+if (enc_rcon > 0xA) {
     // Invalid opcode.
     throw trap_illegal_instruction(0);
 }
@@ -19,7 +19,7 @@ uint32_t    temp              = (RS1 >> 32) & 0xFFFFFFFF  ;
 uint8_t     rcon              = 0            ;
 uint64_t    result                           ;
 
-if(enc_rcon != 0xA) {
+if (enc_rcon != 0xA) {
     temp    = (temp >> 8) | (temp << 24); // Rotate right by 8
     rcon    = round_consts[enc_rcon];
 }

riscv/insns/beq.h

@@ -1,2 +1,2 @@
-if(RS1 == RS2)
+if (RS1 == RS2)
   set_pc(BRANCH_TARGET);

riscv/insns/bge.h

@@ -1,2 +1,2 @@
-if(sreg_t(RS1) >= sreg_t(RS2))
+if (sreg_t(RS1) >= sreg_t(RS2))
   set_pc(BRANCH_TARGET);

riscv/insns/bgeu.h

@@ -1,2 +1,2 @@
-if(RS1 >= RS2)
+if (RS1 >= RS2)
   set_pc(BRANCH_TARGET);

riscv/insns/blt.h

@@ -1,2 +1,2 @@
-if(sreg_t(RS1) < sreg_t(RS2))
+if (sreg_t(RS1) < sreg_t(RS2))
   set_pc(BRANCH_TARGET);

riscv/insns/bltu.h

@@ -1,2 +1,2 @@
-if(RS1 < RS2)
+if (RS1 < RS2)
   set_pc(BRANCH_TARGET);

riscv/insns/bne.h

@@ -1,2 +1,2 @@
-if(RS1 != RS2)
+if (RS1 != RS2)
   set_pc(BRANCH_TARGET);

riscv/insns/div.h

@@ -1,9 +1,9 @@
 require_extension('M');
 sreg_t lhs = sext_xlen(RS1);
 sreg_t rhs = sext_xlen(RS2);
-if(rhs == 0)
+if (rhs == 0)
   WRITE_RD(UINT64_MAX);
-else if(lhs == INT64_MIN && rhs == -1)
+else if (lhs == INT64_MIN && rhs == -1)
   WRITE_RD(lhs);
 else
   WRITE_RD(sext_xlen(lhs / rhs));

riscv/insns/divu.h

@@ -1,7 +1,7 @@
 require_extension('M');
 reg_t lhs = zext_xlen(RS1);
 reg_t rhs = zext_xlen(RS2);
-if(rhs == 0)
+if (rhs == 0)
   WRITE_RD(UINT64_MAX);
 else
   WRITE_RD(sext_xlen(lhs / rhs));

riscv/insns/divuw.h

@@ -2,7 +2,7 @@ require_extension('M');
 require_rv64;
 reg_t lhs = zext32(RS1);
 reg_t rhs = zext32(RS2);
-if(rhs == 0)
+if (rhs == 0)
   WRITE_RD(UINT64_MAX);
 else
   WRITE_RD(sext32(lhs / rhs));

riscv/insns/divw.h

@@ -2,7 +2,7 @@ require_extension('M');
 require_rv64;
 sreg_t lhs = sext32(RS1);
 sreg_t rhs = sext32(RS2);
-if(rhs == 0)
+if (rhs == 0)
   WRITE_RD(UINT64_MAX);
 else
   WRITE_RD(sext32(lhs / rhs));

riscv/insns/kmmawb2.h

@@ -3,7 +3,7 @@ P_LOOP(32, {
   int64_t addop = 0;
   int64_t mres = 0;
   bool sat = false;
-  if((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) {
+  if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) {
     mres = ((int64_t) ps1 * P_SH(ps2, 0)) << 1;
     addop = mres >> 16;
   } else {

riscv/insns/kmmawb2_u.h

@@ -3,7 +3,7 @@ P_LOOP(32, {
   int64_t addop = 0;
   int64_t mres = 0;
   bool sat = false;
-  if((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) {
+  if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) {
     mres = ((int64_t) ps1 * P_SH(ps2, 0)) << 1;
     addop = ((mres >> 15) + 1) >> 1;
   } else {

riscv/insns/kmmawt2.h

@@ -3,7 +3,7 @@ P_LOOP(32, {
   int64_t addop = 0;
   int64_t mres = 0;
   bool sat = false;
-  if((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) {
+  if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) {
     mres = ((int64_t) ps1 *  P_SH(ps2, 1)) << 1;
     addop = mres >> 16;
   } else {

riscv/insns/kmmawt2_u.h

@@ -3,7 +3,7 @@ P_LOOP(32, {
   int64_t addop = 0;
   int64_t mres = 0;
   bool sat = false;
-  if((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) {
+  if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) {
     mres = ((int64_t) ps1 *  P_SH(ps2, 1)) << 1;
     addop = ((mres >> 15) + 1) >> 1;
   } else {

riscv/insns/kmmwb2.h

@@ -1,6 +1,6 @@
 require_vector_vs;
 P_LOOP(32, {
-  if((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) {
+  if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) {
     int64_t mres = ((int64_t) ps1 * P_SH(ps2, 0)) << 1;
     pd = mres >> 16;
   } else {

riscv/insns/kmmwb2_u.h

@@ -1,6 +1,6 @@
 require_vector_vs;
 P_LOOP(32, {
-  if((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) {
+  if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 0))) {
     int64_t mres = ((int64_t) ps1 * P_SH(ps2, 0)) << 1;
     pd = ((mres >> 15) + 1) >> 1;
   } else {

riscv/insns/kmmwt2.h

@@ -1,6 +1,6 @@
 require_vector_vs;
 P_LOOP(32, {
-  if((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) {
+  if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) {
     int64_t mres = ((int64_t) ps1 * P_SH(ps2, 1)) << 1;
     pd = mres >> 16;
   } else {

riscv/insns/kmmwt2_u.h

@@ -1,6 +1,6 @@
 require_vector_vs;
 P_LOOP(32, {
-  if((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) {
+  if ((INT32_MIN != ps1) | (INT16_MIN != P_SH(ps2, 1))) {
     int64_t mres = ((int64_t) ps1 * P_SH(ps2, 1)) << 1;
     pd = ((mres >> 15) + 1) >> 1;
   } else {

riscv/insns/kslra16_u.h

@@ -3,7 +3,7 @@ P_X_LOOP(16, 5, {
   if (ssa < 0) {
     sa = -ssa;
     sa = (sa == 16) ? 15 : sa;
-    if(sa != 0)
+    if (sa != 0)
       pd = ((ps1 >> (sa - 1)) + 1) >> 1;
     else
       pd = ps1;

riscv/insns/kslra32_u.h

@@ -4,7 +4,7 @@ P_X_LOOP(32, 6, {
   if (ssa < 0) {
     sa = -ssa;
     sa = (sa == 32) ? 31 : sa;
-    if(sa != 0)
+    if (sa != 0)
       pd = ((ps1 >> (sa - 1)) + 1) >> 1;
     else
       pd = ps1;

riscv/insns/kslra8_u.h

@@ -3,7 +3,7 @@ P_X_LOOP(8, 4, {
   if (ssa < 0) {
     sa = -ssa;
     sa = (sa == 8) ? 7 : sa;
-    if(sa != 0)
+    if (sa != 0)
       pd = ((ps1 >> (sa - 1)) + 1) >> 1;
     else
       pd = ps1;

riscv/insns/kwmmul.h

@@ -1,6 +1,6 @@
 require_vector_vs;
 P_LOOP(32, {
-  if((INT32_MIN != ps1) | (INT32_MIN != ps2)) {
+  if ((INT32_MIN != ps1) | (INT32_MIN != ps2)) {
     int64_t mres = ((int64_t) ps1 * (int64_t) ps2) << 1;
     pd = mres >> 32;
   } else {

riscv/insns/kwmmul_u.h

@@ -1,6 +1,6 @@
 require_vector_vs;
 P_LOOP(32, {
-  if((INT32_MIN != ps1) | (INT32_MIN != ps2)) {
+  if ((INT32_MIN != ps1) | (INT32_MIN != ps2)) {
     int64_t mres = ((int64_t) ps1 * (int64_t) ps2) << 1;
     pd = ((mres >> 31) + 1) >> 1;
   } else {

riscv/insns/rem.h

@@ -1,9 +1,9 @@
 require_extension('M');
 sreg_t lhs = sext_xlen(RS1);
 sreg_t rhs = sext_xlen(RS2);
-if(rhs == 0)
+if (rhs == 0)
   WRITE_RD(lhs);
-else if(lhs == INT64_MIN && rhs == -1)
+else if (lhs == INT64_MIN && rhs == -1)
   WRITE_RD(0);
 else
   WRITE_RD(sext_xlen(lhs % rhs));

riscv/insns/remu.h

@@ -1,7 +1,7 @@
 require_extension('M');
 reg_t lhs = zext_xlen(RS1);
 reg_t rhs = zext_xlen(RS2);
-if(rhs == 0)
+if (rhs == 0)
   WRITE_RD(sext_xlen(RS1));
 else
   WRITE_RD(sext_xlen(lhs % rhs));

riscv/insns/remuw.h

@@ -2,7 +2,7 @@ require_extension('M');
 require_rv64;
 reg_t lhs = zext32(RS1);
 reg_t rhs = zext32(RS2);
-if(rhs == 0)
+if (rhs == 0)
   WRITE_RD(sext32(lhs));
 else
   WRITE_RD(sext32(lhs % rhs));

riscv/insns/remw.h

@@ -2,7 +2,7 @@ require_extension('M');
 require_rv64;
 sreg_t lhs = sext32(RS1);
 sreg_t rhs = sext32(RS2);
-if(rhs == 0)
+if (rhs == 0)
   WRITE_RD(lhs);
 else
   WRITE_RD(sext32(lhs % rhs));

riscv/insns/rsub64.h

@@ -2,7 +2,7 @@ P_64_PROFILE({
   rd = (rs1 - rs2) >> 1;
   if (rs1 > 0 && rs2 < 0) {
     rd &= ~((reg_t)1 << 63);
-  } else if(rs1 < 0 && rs2 > 0) {
+  } else if (rs1 < 0 && rs2 > 0) {
     rd |= ((reg_t)1 << 63);
   }
 })

riscv/insns/sra16_u.h

@@ -1,5 +1,5 @@
 P_X_LOOP(16, 4, {
-  if(sa > 0)
+  if (sa > 0)
     pd = ((ps1 >> (sa - 1)) + 1) >> 1;
   else
     pd = ps1;

riscv/insns/sra32_u.h

@@ -1,6 +1,6 @@
 require_rv64;
 P_X_LOOP(32, 5, {
-  if(sa > 0)
+  if (sa > 0)
     pd = (((uint64_t)(ps1 >> (sa - 1))) + 1) >> 1;
   else
     pd = ps1;

riscv/insns/sra8_u.h

@@ -1,5 +1,5 @@
 P_X_LOOP(8, 3, {
-  if(sa > 0)
+  if (sa > 0)
     pd = ((ps1 >> (sa - 1)) + 1) >> 1;
   else
     pd = ps1;

riscv/insns/vdiv_vx.h

@@ -1,9 +1,9 @@
 // vdiv.vx vd, vs2, rs1
 VI_VX_LOOP
 ({
-  if(rs1 == 0)
+  if (rs1 == 0)
     vd = -1;
-  else if(vs2 == (INT64_MIN >> (64 - sew)) && rs1 == -1)
+  else if (vs2 == (INT64_MIN >> (64 - sew)) && rs1 == -1)
     vd = vs2;
   else
     vd = vs2 / rs1;

riscv/insns/vdivu_vv.h

@@ -1,7 +1,7 @@
 // vdivu.vv vd, vs2, vs1
 VI_VV_ULOOP
 ({
-  if(vs1 == 0)
+  if (vs1 == 0)
     vd = -1;
   else
     vd = vs2 / vs1;

riscv/insns/vdivu_vx.h

@@ -1,7 +1,7 @@
 // vdivu.vx vd, vs2, rs1
 VI_VX_ULOOP
 ({
-  if(rs1 == 0)
+  if (rs1 == 0)
     vd = -1;
   else
     vd = vs2 / rs1;

riscv/insns/vfmv_f_s.h

@@ -9,7 +9,7 @@ require(STATE.frm->read() < 0x5);
 reg_t rs2_num = insn.rs2();
 uint64_t vs2_0 = 0;
 const reg_t sew = P.VU.vsew;
-switch(sew) {
+switch (sew) {
   case e16:
     vs2_0 = P.VU.elt<uint16_t>(rs2_num, 0);
     break;

riscv/insns/vfmv_s_f.h

@@ -11,7 +11,7 @@ reg_t vl = P.VU.vl->read();
 if (vl > 0 && P.VU.vstart->read() < vl) {
   reg_t rd_num = insn.rd();
 
-  switch(P.VU.vsew) {
+  switch (P.VU.vsew) {
     case e16:
       P.VU.elt<uint16_t>(rd_num, 0, true) = f16(FRS1).v;
       break;

riscv/insns/vmsbf_m.h

@@ -24,7 +24,7 @@ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) {
     uint64_t res = 0;
     if (!has_one && !vs2_lsb) {
       res = 1;
-    } else if(!has_one && vs2_lsb) {
+    } else if (!has_one && vs2_lsb) {
       has_one = true;
     }
     vd = (vd & ~mmask) | ((res << mpos) & mmask);

riscv/insns/vmsif_m.h

@@ -23,7 +23,7 @@ for (reg_t i = P.VU.vstart->read(); i < vl; ++i) {
     uint64_t res = 0;
     if (!has_one && !vs2_lsb) {
       res = 1;
-    } else if(!has_one && vs2_lsb) {
+    } else if (!has_one && vs2_lsb) {
       has_one = true;
       res = 1;
     }

riscv/insns/vmsof_m.h

@@ -21,7 +21,7 @@ for (reg_t i = P.VU.vstart->read() ; i < vl; ++i) {
   if (insn.v_vm() == 1 || (insn.v_vm() == 0 && do_mask)) {
     uint64_t &vd = P.VU.elt<uint64_t>(rd_num, midx, true);
     uint64_t res = 0;
-    if(!has_one && vs2_lsb) {
+    if (!has_one && vs2_lsb) {
       has_one = true;
       res = 1;
     }

riscv/insns/vmv_s_x.h

@@ -8,7 +8,7 @@ if (vl > 0 && P.VU.vstart->read() < vl) {
   reg_t rd_num = insn.rd();
   reg_t sew = P.VU.vsew;
 
-  switch(sew) {
+  switch (sew) {
   case e8:
     P.VU.elt<uint8_t>(rd_num, 0, true) = RS1;
     break;

riscv/insns/vmv_x_s.h

@@ -6,7 +6,7 @@ reg_t rs1 = RS1;
 reg_t sew = P.VU.vsew;
 reg_t rs2_num = insn.rs2();
 
-switch(sew) {
+switch (sew) {
 case e8:
   WRITE_RD(P.VU.elt<int8_t>(rs2_num, 0));
   break;

riscv/insns/vrem_vv.h

@@ -3,7 +3,7 @@ VI_VV_LOOP
 ({
   if (vs1 == 0)
     vd = vs2;
-  else if(vs2 == -(((intmax_t)1) << (sew - 1)) && vs1 == -1)
+  else if (vs2 == -(((intmax_t)1) << (sew - 1)) && vs1 == -1)
     vd = 0;
   else {
     vd = vs2 % vs1;

riscv/insns/vsadd_vi.h

@@ -2,7 +2,7 @@
 VI_CHECK_SSS(false);
 VI_LOOP_BASE
 bool sat = false;
-switch(sew) {
+switch (sew) {
 case e8: {
   VI_PARAMS(e8);
   vd = sat_add<int8_t, uint8_t>(vs2, vsext(simm5, sew), sat);

riscv/insns/vsadd_vv.h

@@ -2,7 +2,7 @@
 VI_CHECK_SSS(true);
 VI_LOOP_BASE
 bool sat = false;
-switch(sew) {
+switch (sew) {
 case e8: {
   VV_PARAMS(e8);
   vd = sat_add<int8_t, uint8_t>(vs2, vs1, sat);

riscv/insns/vsadd_vx.h

@@ -2,7 +2,7 @@
 VI_CHECK_SSS(false);
 VI_LOOP_BASE
 bool sat = false;
-switch(sew) {
+switch (sew) {
 case e8: {
   VX_PARAMS(e8);
   vd = sat_add<int8_t, uint8_t>(vs2, rs1, sat);

riscv/insns/vslide1up_vx.h

@@ -6,24 +6,24 @@ if (i != 0) {
   if (sew == e8) {
     VI_XI_SLIDEUP_PARAMS(e8, 1);
     vd = vs2;
-  } else if(sew == e16) {
+  } else if (sew == e16) {
     VI_XI_SLIDEUP_PARAMS(e16, 1);
     vd = vs2;
-  } else if(sew == e32) {
+  } else if (sew == e32) {
     VI_XI_SLIDEUP_PARAMS(e32, 1);
     vd = vs2;
-  } else if(sew == e64) {
+  } else if (sew == e64) {
     VI_XI_SLIDEUP_PARAMS(e64, 1);
     vd = vs2;
   }
 } else {
   if (sew == e8) {
     P.VU.elt<uint8_t>(rd_num, 0, true) = RS1;
-  } else if(sew == e16) {
+  } else if (sew == e16) {
     P.VU.elt<uint16_t>(rd_num, 0, true) = RS1;
-  } else if(sew == e32) {
+  } else if (sew == e32) {
     P.VU.elt<uint32_t>(rd_num, 0, true) = RS1;
-  } else if(sew == e64) {
+  } else if (sew == e64) {
     P.VU.elt<uint64_t>(rd_num, 0, true) = RS1;
   }
 }

riscv/interactive.cc

@@ -271,7 +271,7 @@ reg_t sim_t::get_pc(const std::vector<std::string>& args)
 
 void sim_t::interactive_pc(const std::string& cmd, const std::vector<std::string>& args)
 {
-  if(args.size() != 1)
+  if (args.size() != 1)
     throw trap_interactive();
 
   processor_t *p = get_core(args[0]);
@@ -309,7 +309,7 @@ reg_t sim_t::get_reg(const std::vector<std::string>& args)
 
 freg_t sim_t::get_freg(const std::vector<std::string>& args, int size)
 {
-  if(args.size() != 2)
+  if (args.size() != 2)
     throw trap_interactive();
 
   processor_t *p = get_core(args[0]);
@@ -363,9 +363,9 @@ void sim_t::interactive_vreg(const std::string& cmd, const std::vector<std::stri
 
   for (int r = rstart; r < rend; ++r) {
     out << std::setfill (' ') << std::left << std::setw(4) << vr_name[r] << std::right << ": ";
-    for (int e = num_elem-1; e >= 0; --e){
+    for (int e = num_elem-1; e >= 0; --e) {
       uint64_t val;
-      switch(elen){
+      switch (elen) {
         case 8:
           val = p->VU.elt<uint64_t>(r, e);
           out << std::dec << "[" << e << "]: 0x" << std::hex << std::setfill ('0') << std::setw(16) << val << "  ";
@@ -475,7 +475,7 @@ reg_t sim_t::get_mem(const std::vector<std::string>& args)
   if (addr == LONG_MAX)
     addr = strtoul(addr_str.c_str(),NULL,16);
 
-  switch(addr % 8)
+  switch (addr % 8)
   {
     case 0:
       val = mmu->load_uint64(addr);
@@ -522,7 +522,7 @@ void sim_t::interactive_str(const std::string& cmd, const std::vector<std::strin
   std::ostream out(sout_.rdbuf());
 
   char ch;
-  while((ch = mmu->load_uint8(addr++)))
+  while ((ch = mmu->load_uint8(addr++)))
     out << ch;
 
   out << std::endl;

riscv/isa_parser.h

@@ -69,7 +69,7 @@ typedef enum {
 class isa_parser_t {
 public:
   isa_parser_t(const char* str, const char *priv);
-  ~isa_parser_t(){};
+  ~isa_parser_t() {};
   unsigned get_max_xlen() const { return max_xlen; }
   reg_t get_max_isa() const { return max_isa; }
   std::string get_isa_string() const { return isa_string; }

riscv/processor.h

@@ -406,7 +406,7 @@ public:
 
       // vector element for varies SEW
       template<class T>
-        T& elt(reg_t vReg, reg_t n, bool is_write = false){
+        T& elt(reg_t vReg, reg_t n, bool is_write = false) {
           assert(vsew != 0);
           assert((VLEN >> 3)/sizeof(T) > 0);
           reg_t elts_per_reg = (VLEN >> 3) / (sizeof(T));
@@ -453,7 +453,7 @@ public:
         vstart_alu(false) {
       }
 
-      ~vectorUnit_t(){
+      ~vectorUnit_t() {
         free(reg_file);
         reg_file = 0;
       }