Support Ziccid extension

disasm/isa_parser.cc

@@ -140,6 +140,8 @@ isa_parser_t::isa_parser_t(const char* str, const char *priv)
       // HINTs encoded in base-ISA instructions are always present.
     } else if (ext_str == "zihintntl") {
       // HINTs encoded in base-ISA instructions are always present.
+    } else if (ext_str == "ziccid") {
+      extension_table[EXT_ZICCID] = true;
     } else if (ext_str == "ziccif") {
       // aligned instruction fetch is always atomic in Spike
     } else if (ext_str == "zaamo") {

riscv/execute.cc

@@ -210,6 +210,8 @@ bool processor_t::slow_path() const
 // fetch/decode/execute loop
 void processor_t::step(size_t n)
 {
+  mmu_t* _mmu = mmu;
+
   if (!state.debug_mode) {
     if (halt_request == HR_REGULAR) {
       enter_debug_mode(DCSR_CAUSE_DEBUGINT, 0);
@@ -221,10 +223,15 @@ void processor_t::step(size_t n)
     }
   }
 
+  if (extension_enabled(EXT_ZICCID)) {
+    // Ziccid requires stores eventually become visible to instruction fetch,
+    // so periodically flush the I$
+    _mmu->flush_icache();
+  }
+
   while (n > 0) {
     size_t instret = 0;
     reg_t pc = state.pc;
-    mmu_t* _mmu = mmu;
     state.prv_changed = false;
     state.v_changed = false;
 

riscv/isa_parser.h

@@ -50,6 +50,7 @@ typedef enum {
   EXT_ZFINX,
   EXT_ZHINX,
   EXT_ZHINXMIN,
+  EXT_ZICCID,
   EXT_ZICBOM,
   EXT_ZICBOZ,
   EXT_ZICNTR,