[xcc, sim] changed instruction format so imm12 subs for rs2

config.h.in

@@ -24,5 +24,11 @@
 /* Define if libopcodes exists */
 #undef RISCV_HAVE_LIBOPCODES
 
+/* Define if subproject MCPPBS_SPROJ_NORM is enabled */
+#undef SOFTFLOAT_ENABLED
+
+/* Define if subproject MCPPBS_SPROJ_NORM is enabled */
+#undef SOFTFLOAT_RISCV_ENABLED
+
 /* Define to 1 if you have the ANSI C header files. */
 #undef STDC_HEADERS

riscv/decode.h

@@ -78,10 +78,10 @@ const int JUMP_ALIGN_BITS = 1;
 // note: bit fields are in little-endian order
 struct itype_t
 {
-  unsigned imm : IMM_BITS;
+  unsigned imm12 : IMM_BITS;
   unsigned funct : FUNCT_BITS;
-  unsigned rb : GPRID_BITS;
-  unsigned ra : GPRID_BITS;
+  unsigned rs1 : GPRID_BITS;
+  unsigned rdi : GPRID_BITS;
   unsigned opcode : OPCODE_BITS;
 };
 
@@ -93,28 +93,28 @@ struct jtype_t
 
 struct rtype_t
 {
-  unsigned rc : GPRID_BITS;
+  unsigned rdr : GPRID_BITS;
   unsigned functr : FUNCTR_BITS;
   unsigned funct : FUNCT_BITS;
-  unsigned rb : GPRID_BITS;
-  unsigned ra : GPRID_BITS;
+  unsigned rs1 : GPRID_BITS;
+  unsigned rs2 : GPRID_BITS;
   unsigned opcode : OPCODE_BITS;
 };
 
 struct btype_t
 {
   unsigned bigimm : BIGIMM_BITS;
-  unsigned rt : GPRID_BITS;
+  unsigned rdi : GPRID_BITS;
   unsigned opcode : OPCODE_BITS;
 };
 
 struct ftype_t
 {
-  unsigned rc : FPRID_BITS;
-  unsigned rd : FPRID_BITS;
+  unsigned rdr : FPRID_BITS;
+  unsigned rs3 : FPRID_BITS;
   unsigned ffunct : FFUNCT_BITS;
-  unsigned rb : FPRID_BITS;
-  unsigned ra : FPRID_BITS;
+  unsigned rs1 : FPRID_BITS;
+  unsigned rs2 : FPRID_BITS;
   unsigned opcode : OPCODE_BITS;
 };
 
@@ -129,18 +129,20 @@ union insn_t
 };
 
 // helpful macros, etc
-#define RA R[insn.rtype.ra]
-#define RB R[insn.rtype.rb]
-#define RC R[insn.rtype.rc]
-#define FRA FR[insn.ftype.ra]
-#define FRB FR[insn.ftype.rb]
-#define FRC FR[insn.ftype.rc]
-#define FRD FR[insn.ftype.rd]
+#define RS1 R[insn.rtype.rs1]
+#define RS2 R[insn.rtype.rs2]
+#define RDR R[insn.rtype.rdr]
+#define RDI R[insn.itype.rdi]
+#define FRS1 FR[insn.ftype.rs1]
+#define FRS2 FR[insn.ftype.rs2]
+#define FRS3 FR[insn.ftype.rs3]
+#define FRDR FR[insn.ftype.rdr]
+#define FRDI FR[insn.itype.rdi]
 #define BIGIMM insn.btype.bigimm
-#define IMM insn.itype.imm
-#define SIMM ((int32_t)((uint32_t)insn.itype.imm<<(32-IMM_BITS))>>(32-IMM_BITS))
-#define SHAMT (insn.itype.imm & 0x3F)
-#define SHAMTW (insn.itype.imm & 0x1F)
+#define IMM insn.itype.imm12
+#define SIMM ((int32_t)((uint32_t)insn.itype.imm12<<(32-IMM_BITS))>>(32-IMM_BITS))
+#define SHAMT (insn.itype.imm12 & 0x3F)
+#define SHAMTW (insn.itype.imm12 & 0x1F)
 #define TARGET insn.jtype.target
 #define BRANCH_TARGET (npc + (SIMM << BRANCH_ALIGN_BITS))
 #define JUMP_TARGET ((npc & ~((1<<(TARGET_BITS+JUMP_ALIGN_BITS))-1)) + (TARGET << JUMP_ALIGN_BITS))

riscv/execute.h

@@ -77,12 +77,12 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/sgninj_s.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd00004c0)
+        if((insn.bits & 0xfff07fe0) == 0xd00004c0)
         {
           #include "insns/cvt_s_w.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0000440)
+        if((insn.bits & 0xfff07fe0) == 0xd0000440)
         {
           #include "insns/trunc_w_s.h"
           break;
@@ -97,22 +97,22 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/sgninjn_s.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0000400)
+        if((insn.bits & 0xfff07fe0) == 0xd0000400)
         {
           #include "insns/trunc_l_s.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd00004e0)
+        if((insn.bits & 0xfff07fe0) == 0xd00004e0)
         {
           #include "insns/cvtu_s_w.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0000420)
+        if((insn.bits & 0xfff07fe0) == 0xd0000420)
         {
           #include "insns/truncu_l_s.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd00004a0)
+        if((insn.bits & 0xfff07fe0) == 0xd00004a0)
         {
           #include "insns/cvtu_s_l.h"
           break;
@@ -122,7 +122,7 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/sub_s.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0000080)
+        if((insn.bits & 0xfff07fe0) == 0xd0000080)
         {
           #include "insns/sqrt_s.h"
           break;
@@ -137,7 +137,7 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/sgnmul_s.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0000480)
+        if((insn.bits & 0xfff07fe0) == 0xd0000480)
         {
           #include "insns/cvt_s_l.h"
           break;
@@ -147,7 +147,7 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/div_s.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0000660)
+        if((insn.bits & 0xfff07fe0) == 0xd0000660)
         {
           #include "insns/cvt_s_d.h"
           break;
@@ -162,7 +162,7 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/mul_s.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0000460)
+        if((insn.bits & 0xfff07fe0) == 0xd0000460)
         {
           #include "insns/truncu_w_s.h"
           break;
@@ -186,17 +186,17 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/c_eq_d.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd00064a0)
+        if((insn.bits & 0xfff07fe0) == 0xd00064a0)
         {
           #include "insns/cvtu_d_l.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0006440)
+        if((insn.bits & 0xfff07fe0) == 0xd0006440)
         {
           #include "insns/trunc_w_d.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd00064e0)
+        if((insn.bits & 0xfff07fe0) == 0xd00064e0)
         {
           #include "insns/cvtu_d_w.h"
           break;
@@ -221,17 +221,17 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/sgninjn_d.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0006600)
+        if((insn.bits & 0xfff07fe0) == 0xd0006600)
         {
           #include "insns/cvt_d_s.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0006400)
+        if((insn.bits & 0xfff07fe0) == 0xd0006400)
         {
           #include "insns/trunc_l_d.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0006420)
+        if((insn.bits & 0xfff07fe0) == 0xd0006420)
         {
           #include "insns/truncu_l_d.h"
           break;
@@ -241,22 +241,22 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/sub_d.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0006080)
+        if((insn.bits & 0xfff07fe0) == 0xd0006080)
         {
           #include "insns/sqrt_d.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd00064c0)
+        if((insn.bits & 0xfff07fe0) == 0xd00064c0)
         {
           #include "insns/cvt_d_w.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0006480)
+        if((insn.bits & 0xfff07fe0) == 0xd0006480)
         {
           #include "insns/cvt_d_l.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd0006460)
+        if((insn.bits & 0xfff07fe0) == 0xd0006460)
         {
           #include "insns/truncu_w_d.h"
           break;
@@ -317,12 +317,12 @@ switch((insn.bits >> 0x19) & 0x7f)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe0fffe0) == 0xd4000000)
+        if((insn.bits & 0xfff07fe0) == 0xd4000000)
         {
           #include "insns/mff_s.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd4000800)
+        if((insn.bits & 0xfff07fe0) == 0xd4000800)
         {
           #include "insns/mtf_s.h"
           break;
@@ -331,12 +331,12 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x6:
       {
-        if((insn.bits & 0xfe0fffe0) == 0xd4006000)
+        if((insn.bits & 0xfff07fe0) == 0xd4006000)
         {
           #include "insns/mff_d.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd4006400)
+        if((insn.bits & 0xfff07fe0) == 0xd4006400)
         {
           #include "insns/mffh_d.h"
           break;
@@ -346,7 +346,7 @@ switch((insn.bits >> 0x19) & 0x7f)
           #include "insns/mtflh_d.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd4006800)
+        if((insn.bits & 0xfff07fe0) == 0xd4006800)
         {
           #include "insns/mtf_d.h"
           break;
@@ -947,17 +947,17 @@ switch((insn.bits >> 0x19) & 0x7f)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe0fffe0) == 0xf6000000)
+        if((insn.bits & 0xfff07fe0) == 0xf6000000)
         {
           #include "insns/jalr_c.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xf6000040)
+        if((insn.bits & 0xfff07fe0) == 0xf6000040)
         {
           #include "insns/jalr_j.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xf6000020)
+        if((insn.bits & 0xfff07fe0) == 0xf6000020)
         {
           #include "insns/jalr_r.h"
           break;
@@ -975,7 +975,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x2:
       {
-        if((insn.bits & 0xfff07fe0) == 0xf6002000)
+        if((insn.bits & 0xfe0fffe0) == 0xf6002000)
         {
           #include "insns/mfcr.h"
           break;
@@ -1058,7 +1058,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x4:
       {
-        if((insn.bits & 0xfff07fe0) == 0xfc004000)
+        if((insn.bits & 0xfe0fffe0) == 0xfc004000)
         {
           #include "insns/mfpcr.h"
           break;

riscv/insns/add.h

@@ -1,2 +1,2 @@
 require64;
-RC = RA + RB;
+RDR = RS1 + RS2;

riscv/insns/add_d.h

@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_add(FRA, FRB);
+FRDR = f64_add(FRS1, FRS2);
 set_fp_exceptions;

riscv/insns/add_s.h

@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_add(FRA, FRB);
+FRDR = f32_add(FRS1, FRS2);
 set_fp_exceptions;

riscv/insns/addi.h

@@ -1,2 +1,2 @@
 require64;
-RA = SIMM + RB;
+RDI = SIMM + RS1;

riscv/insns/addiw.h

@@ -1 +1 @@
-RA = sext32(SIMM + RB);
+RDI = sext32(SIMM + RS1);

riscv/insns/addw.h

@@ -1,2 +1,2 @@
-RC = sext32(RA + RB);
+RDR = sext32(RS1 + RS2);
 

riscv/insns/amo_add.h

@@ -1,4 +1,4 @@
 require64;
-reg_t v = mmu.load_uint64(RB);
-mmu.store_uint64(RB, RA + v);
-RC = v;
+reg_t v = mmu.load_uint64(RS1);
+mmu.store_uint64(RS1, RS2 + v);
+RDR = v;

riscv/insns/amo_and.h

@@ -1,4 +1,4 @@
 require64;
-reg_t v = mmu.load_uint64(RB);
-mmu.store_uint64(RB, RA & v);
-RC = v;
+reg_t v = mmu.load_uint64(RS1);
+mmu.store_uint64(RS1, RS2 & v);
+RDR = v;

riscv/insns/amo_max.h

@@ -1,4 +1,4 @@
 require64;
-sreg_t v = mmu.load_int64(RB);
-mmu.store_uint64(RB, std::max(sreg_t(RA),v));
-RC = v;
+sreg_t v = mmu.load_int64(RS1);
+mmu.store_uint64(RS1, std::max(sreg_t(RS2),v));
+RDR = v;

riscv/insns/amo_maxu.h

@@ -1,4 +1,4 @@
 require64;
-reg_t v = mmu.load_uint64(RB);
-mmu.store_uint64(RB, std::max(RA,v));
-RC = v;
+reg_t v = mmu.load_uint64(RS1);
+mmu.store_uint64(RS1, std::max(RS2,v));
+RDR = v;

riscv/insns/amo_min.h

@@ -1,4 +1,4 @@
 require64;
-sreg_t v = mmu.load_int64(RB);
-mmu.store_uint64(RB, std::min(sreg_t(RA),v));
-RC = v;
+sreg_t v = mmu.load_int64(RS1);
+mmu.store_uint64(RS1, std::min(sreg_t(RS2),v));
+RDR = v;

riscv/insns/amo_minu.h

@@ -1,4 +1,4 @@
 require64;
-reg_t v = mmu.load_uint64(RB);
-mmu.store_uint64(RB, std::min(RA,v));
-RC = v;
+reg_t v = mmu.load_uint64(RS1);
+mmu.store_uint64(RS1, std::min(RS2,v));
+RDR = v;

riscv/insns/amo_or.h

@@ -1,4 +1,4 @@
 require64;
-reg_t v = mmu.load_uint64(RB);
-mmu.store_uint64(RB, RA | v);
-RC = v;
+reg_t v = mmu.load_uint64(RS1);
+mmu.store_uint64(RS1, RS2 | v);
+RDR = v;

riscv/insns/amo_swap.h

@@ -1,4 +1,4 @@
 require64;
-reg_t v = mmu.load_uint64(RB);
-mmu.store_uint64(RB, RA);
-RC = v;
+reg_t v = mmu.load_uint64(RS1);
+mmu.store_uint64(RS1, RS2);
+RDR = v;

riscv/insns/amow_add.h

@@ -1,3 +1,3 @@
-reg_t v = mmu.load_int32(RB);
-mmu.store_uint32(RB, RA + v);
-RC = v;
+reg_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, RS2 + v);
+RDR = v;

riscv/insns/amow_and.h

@@ -1,3 +1,3 @@
-reg_t v = mmu.load_int32(RB);
-mmu.store_uint32(RB, RA & v);
-RC = v;
+reg_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, RS2 & v);
+RDR = v;

riscv/insns/amow_max.h

@@ -1,3 +1,3 @@
-int32_t v = mmu.load_int32(RB);
-mmu.store_uint32(RB, std::max(int32_t(RA),v));
-RC = v;
+int32_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, std::max(int32_t(RS2),v));
+RDR = v;

riscv/insns/amow_maxu.h

@@ -1,3 +1,3 @@
-uint32_t v = mmu.load_int32(RB);
-mmu.store_uint32(RB, std::max(uint32_t(RA),v));
-RC = v;
+uint32_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, std::max(uint32_t(RS2),v));
+RDR = v;

riscv/insns/amow_min.h

@@ -1,3 +1,3 @@
-int32_t v = mmu.load_int32(RB);
-mmu.store_uint32(RB, std::min(int32_t(RA),v));
-RC = v;
+int32_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, std::min(int32_t(RS2),v));
+RDR = v;

riscv/insns/amow_minu.h

@@ -1,3 +1,3 @@
-uint32_t v = mmu.load_int32(RB);
-mmu.store_uint32(RB, std::min(uint32_t(RA),v));
-RC = v;
+uint32_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, std::min(uint32_t(RS2),v));
+RDR = v;

riscv/insns/amow_or.h

@@ -1,3 +1,3 @@
-reg_t v = mmu.load_int32(RB);
-mmu.store_uint32(RB, RA | v);
-RC = v;
+reg_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, RS2 | v);
+RDR = v;

riscv/insns/amow_swap.h

@@ -1,3 +1,3 @@
-reg_t v = mmu.load_int32(RB);
-mmu.store_uint32(RB, RA);
-RC = v;
+reg_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, RS2);
+RDR = v;

riscv/insns/and.h

@@ -1 +1 @@
-RC = RA & RB;
+RDR = RS1 & RS2;

riscv/insns/andi.h

@@ -1 +1 @@
-RA = IMM & RB;
+RDI = IMM & RS1;

riscv/insns/beq.h

@@ -1,2 +1,2 @@
-if(cmp_trunc(RA) == cmp_trunc(RB))
+if(cmp_trunc(RS1) == cmp_trunc(RS2))
   npc = BRANCH_TARGET;

riscv/insns/bge.h

@@ -1,2 +1,2 @@
-if(sreg_t(cmp_trunc(RA)) >= sreg_t(cmp_trunc(RB)))
+if(sreg_t(cmp_trunc(RS1)) >= sreg_t(cmp_trunc(RS2)))
   npc = BRANCH_TARGET;

riscv/insns/bgeu.h

@@ -1,2 +1,2 @@
-if(cmp_trunc(RA) >= cmp_trunc(RB))
+if(cmp_trunc(RS1) >= cmp_trunc(RS2))
   npc = BRANCH_TARGET;

riscv/insns/blt.h

@@ -1,2 +1,2 @@
-if(sreg_t(cmp_trunc(RA)) < sreg_t(cmp_trunc(RB)))
+if(sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2)))
   npc = BRANCH_TARGET;

riscv/insns/bltu.h

@@ -1,2 +1,2 @@
-if(cmp_trunc(RA) < cmp_trunc(RB))
+if(cmp_trunc(RS1) < cmp_trunc(RS2))
   npc = BRANCH_TARGET;

riscv/insns/bne.h

@@ -1,2 +1,2 @@
-if(cmp_trunc(RA) != cmp_trunc(RB))
+if(cmp_trunc(RS1) != cmp_trunc(RS2))
   npc = BRANCH_TARGET;

riscv/insns/c_eq_d.h

@@ -1,3 +1,3 @@
 require_fp;
-RC = f64_eq(FRA, FRB);
+RDR = f64_eq(FRS1, FRS2);
 set_fp_exceptions;

riscv/insns/c_eq_s.h

@@ -1,3 +1,3 @@
 require_fp;
-RC = f32_eq(FRA, FRB);
+RDR = f32_eq(FRS1, FRS2);
 set_fp_exceptions;

riscv/insns/c_le_d.h

@@ -1,3 +1,3 @@
 require_fp;
-RC = f64_le(FRA, FRB);
+RDR = f64_le(FRS1, FRS2);
 set_fp_exceptions;

riscv/insns/c_le_s.h

@@ -1,3 +1,3 @@
 require_fp;
-RC = f32_le(FRA, FRB);
+RDR = f32_le(FRS1, FRS2);
 set_fp_exceptions;

riscv/insns/c_lt_d.h

@@ -1,3 +1,3 @@
 require_fp;
-RC = f64_lt(FRA, FRB);
+RDR = f64_lt(FRS1, FRS2);
 set_fp_exceptions;

riscv/insns/c_lt_s.h

@@ -1,3 +1,3 @@
 require_fp;
-RC = f32_lt(FRA, FRB);
+RDR = f32_lt(FRS1, FRS2);
 set_fp_exceptions;

riscv/insns/cvt_d_l.h

@@ -1,3 +1,3 @@
 require_fp;
-FRC = i64_to_f64(FRA);
+FRDR = i64_to_f64(FRS1);
 set_fp_exceptions;

riscv/insns/cvt_d_s.h

@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_to_f64(FRA);
+FRDR = f32_to_f64(FRS1);
 set_fp_exceptions;

riscv/insns/cvt_d_w.h

@@ -1,3 +1,3 @@
 require_fp;
-FRC = i32_to_f64(FRA);
+FRDR = i32_to_f64(FRS1);
 set_fp_exceptions;

riscv/insns/cvt_s_d.h

@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_to_f32(FRA);
+FRDR = f64_to_f32(FRS1);
 set_fp_exceptions;

riscv/insns/cvt_s_l.h

@@ -1,3 +1,3 @@
 require_fp;
-FRC = i64_to_f32(FRA);
+FRDR = i64_to_f32(FRS1);
 set_fp_exceptions;

riscv/insns/cvt_s_w.h

@@ -1,3 +1,3 @@
 require_fp;
-FRC = i32_to_f32(FRA);
+FRDR = i32_to_f32(FRS1);
 set_fp_exceptions;

riscv/insns/cvtu_d_l.h

@@ -1,3 +1,3 @@
 require_fp;
-FRC = i64_to_f64(FRA);
+FRDR = i64_to_f64(FRS1);
 set_fp_exceptions;

riscv/insns/cvtu_d_w.h

@@ -1,3 +1,3 @@
 require_fp;
-FRC = ui32_to_f64(FRA);
+FRDR = ui32_to_f64(FRS1);
 set_fp_exceptions;

riscv/insns/cvtu_s_l.h

@@ -1,3 +1,3 @@
 require_fp;
-FRC = i64_to_f32(FRA);
+FRDR = i64_to_f32(FRS1);
 set_fp_exceptions;

riscv/insns/cvtu_s_w.h

@@ -1,3 +1,3 @@
 require_fp;
-FRC = ui32_to_f32(FRA);
+FRDR = ui32_to_f32(FRS1);
 set_fp_exceptions;

riscv/insns/di.h

@@ -1,4 +1,4 @@
 require_supervisor;
 uint32_t temp = sr;
 set_sr(sr & ~SR_ET);
-RC = temp;
+RDR = temp;

riscv/insns/div.h

@@ -1,2 +1,2 @@
 require64;
-RC = sreg_t(RA) / sreg_t(RB);
+RDR = sreg_t(RS1) / sreg_t(RS2);

riscv/insns/div_d.h

@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_div(FRA, FRB);
+FRDR = f64_div(FRS1, FRS2);
 set_fp_exceptions;

riscv/insns/div_s.h

@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_div(FRA, FRB);
+FRDR = f32_div(FRS1, FRS2);
 set_fp_exceptions;

riscv/insns/divu.h

@@ -1,2 +1,2 @@
 require64;
-RC = RA / RB;
+RDR = RS1 / RS2;

riscv/insns/divuw.h

@@ -1,2 +1,2 @@
-RC = sext32(uint32_t(RA)/uint32_t(RB));
+RDR = sext32(uint32_t(RS1)/uint32_t(RS2));
 

riscv/insns/divw.h

@@ -1,2 +1,2 @@
-RC = sext32(int32_t(RA)/int32_t(RB));
+RDR = sext32(int32_t(RS1)/int32_t(RS2));
 

riscv/insns/ei.h

@@ -1,4 +1,4 @@
 require_supervisor;
 uint32_t temp = sr;
 set_sr(sr | SR_ET);
-RC = temp;
+RDR = temp;

riscv/insns/jalr_c.h

@@ -1,3 +1,3 @@
 uint32_t temp = npc;
-npc = RA;
-RC = temp;
+npc = RS1;
+RDR = temp;

riscv/insns/l_d.h

@@ -1,2 +1,2 @@
 require_fp;
-FRA = mmu.load_int64(RB+SIMM);
+FRDI = mmu.load_int64(RS1+SIMM);

riscv/insns/l_s.h

@@ -1,2 +1,2 @@
 require_fp;
-FRA = mmu.load_int32(RB+SIMM);
+FRDI = mmu.load_int32(RS1+SIMM);

riscv/insns/lb.h

@@ -1 +1 @@
-RA = mmu.load_int8(RB+SIMM);
+RDI = mmu.load_int8(RS1+SIMM);

riscv/insns/lbu.h

@@ -1 +1 @@
-RA = mmu.load_uint8(RB+SIMM);
+RDI = mmu.load_uint8(RS1+SIMM);

riscv/insns/ld.h

@@ -1,2 +1,2 @@
 require64;
-RA = mmu.load_int64(RB+SIMM);
+RDI = mmu.load_int64(RS1+SIMM);

riscv/insns/lh.h

@@ -1 +1 @@
-RA = mmu.load_int16(RB+SIMM);
+RDI = mmu.load_int16(RS1+SIMM);

riscv/insns/lhu.h

@@ -1 +1 @@
-RA = mmu.load_uint16(RB+SIMM);
+RDI = mmu.load_uint16(RS1+SIMM);

riscv/insns/lui.h

@@ -1 +1 @@
-RA = sext32(BIGIMM << IMM_BITS);
+RDI = sext32(BIGIMM << IMM_BITS);

riscv/insns/lw.h

@@ -1 +1 @@
-RA = mmu.load_int32(RB+SIMM);
+RDI = mmu.load_int32(RS1+SIMM);

riscv/insns/lwu.h

@@ -1 +1 @@
-RA = mmu.load_uint32(RB+SIMM);
+RDI = mmu.load_uint32(RS1+SIMM);

riscv/insns/madd_d.h

@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_mulAdd(FRA, FRB, FRD);
+FRDR = f64_mulAdd(FRS1, FRS2, FRS3);
 set_fp_exceptions;

riscv/insns/madd_s.h

@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_mulAdd(FRA, FRB, FRD);
+FRDR = f32_mulAdd(FRS1, FRS2, FRS3);
 set_fp_exceptions;

riscv/insns/mfcr.h

@@ -1,6 +1,6 @@
 reg_t val;
 
-switch(insn.rtype.rb)
+switch(insn.rtype.rs2)
 {
   case 0:
     val = fsr;
@@ -18,4 +18,4 @@ switch(insn.rtype.rb)
     val = -1;
 }
 
-RC = gprlen == 64 ? val : sext32(val);
+RDR = gprlen == 64 ? val : sext32(val);

riscv/insns/mff_d.h

@@ -1,3 +1,3 @@
 require64;
 require_fp;
-RC = FRA;
+RDR = FRS1;

riscv/insns/mff_s.h

@@ -1,2 +1,2 @@
 require_fp;
-RC = sext32(FRA);
+RDR = sext32(FRS1);

riscv/insns/mffh_d.h

@@ -1,2 +1,2 @@
 require_fp;
-RC = sext32(FRA >> 32);
+RDR = sext32(FRS1 >> 32);

riscv/insns/mfpcr.h

@@ -2,7 +2,7 @@ require_supervisor;
 
 reg_t val;
 
-switch(insn.rtype.rb)
+switch(insn.rtype.rs2)
 {
   case 0:
     val = sr;
@@ -42,4 +42,4 @@ switch(insn.rtype.rb)
     val = -1;
 }
 
-RC = gprlen == 64 ? val : sext32(val);
+RDR = gprlen == 64 ? val : sext32(val);

riscv/insns/msub_d.h

@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_mulAdd(FRA, FRB, FRD ^ (uint64_t)INT64_MIN);
+FRDR = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN);
 set_fp_exceptions;

riscv/insns/msub_s.h

@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_mulAdd(FRA, FRB, FRD ^ (uint32_t)INT32_MIN);
+FRDR = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN);
 set_fp_exceptions;

riscv/insns/mtcr.h

@@ -1,10 +1,10 @@
-switch(insn.rtype.rb)
+switch(insn.rtype.rs2)
 {
   case 0:
-    set_fsr(RA);
+    set_fsr(RS1);
     break;
 
   case 29:
-    tid = RA;
+    tid = RS1;
     break;
 }

riscv/insns/mtf_d.h

@@ -1,3 +1,3 @@
 require64;
 require_fp;
-FRC = RA;
+FRDR = RS1;

riscv/insns/mtf_s.h

@@ -1,2 +1,2 @@
 require_fp;
-FRC = RA;
+FRDR = RS1;

riscv/insns/mtflh_d.h

@@ -1,2 +1,2 @@
 require_fp;
-FRC = (RA & 0x00000000FFFFFFFF) | (RB << 32);
+FRDR = (RS1 & 0x00000000FFFFFFFF) | (RS2 << 32);

riscv/insns/mtpcr.h

@@ -1,33 +1,33 @@
 require_supervisor;
 
-switch(insn.rtype.rb)
+switch(insn.rtype.rs2)
 {
   case 0:
-    set_sr(RA);
+    set_sr(RS1);
     break;
   case 1:
-    epc = RA;
+    epc = RS1;
     break;
   case 3:
-    ebase = RA & ~0xFFF;
+    ebase = RS1 & ~0xFFF;
     break;
   case 4:
-    count = RA;
+    count = RS1;
     break;
   case 5:
     interrupts_pending &= ~(1 << TIMER_IRQ);
-    compare = RA;
+    compare = RS1;
     break;
 
   case 16:
-    tohost = RA;
-    sim->set_tohost(RA);
+    tohost = RS1;
+    sim->set_tohost(RS1);
     break;
 
   case 24:
-    pcr_k0 = RA;
+    pcr_k0 = RS1;
     break;
   case 25:
-    pcr_k1 = RA;
+    pcr_k1 = RS1;
     break;
 }

riscv/insns/mul.h

@@ -1,2 +1,2 @@
 require64;
-RC = RA * RB;
+RDR = RS1 * RS2;

riscv/insns/mul_d.h

@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_mul(FRA, FRB);
+FRDR = f64_mul(FRS1, FRS2);
 set_fp_exceptions;

riscv/insns/mul_s.h

@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_mul(FRA, FRB);
+FRDR = f32_mul(FRS1, FRS2);
 set_fp_exceptions;

riscv/insns/mulh.h

@@ -1,4 +1,4 @@
 require64;
-int64_t rb = RA;
-int64_t ra = RB;
-RC = (int128_t(rb) * int128_t(ra)) >> 64;
+int64_t rb = RS1;
+int64_t ra = RS2;
+RDR = (int128_t(rb) * int128_t(ra)) >> 64;

riscv/insns/mulhu.h

@@ -1,2 +1,2 @@
 require64;
-RC = (uint128_t(RA) * uint128_t(RB)) >> 64;
+RDR = (uint128_t(RS1) * uint128_t(RS2)) >> 64;

riscv/insns/mulhuw.h

@@ -1,2 +1,2 @@
-RC = sext32((RA * RB) >> 32);
+RDR = sext32((RS1 * RS2) >> 32);
 

riscv/insns/mulhw.h

@@ -1,2 +1,2 @@
-RC = sext32((sreg_t(RA) * sreg_t(RB)) >> 32);
+RDR = sext32((sreg_t(RS1) * sreg_t(RS2)) >> 32);
 

riscv/insns/mulw.h

@@ -1,2 +1,2 @@
-RC = sext32(RA * RB);
+RDR = sext32(RS1 * RS2);
 

riscv/insns/nmadd_d.h

@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_mulAdd(FRA, FRB, FRD) ^ (uint64_t)INT64_MIN;
+FRDR = f64_mulAdd(FRS1, FRS2, FRS3) ^ (uint64_t)INT64_MIN;
 set_fp_exceptions;

riscv/insns/nmadd_s.h

@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_mulAdd(FRA, FRB, FRD) ^ (uint32_t)INT32_MIN;
+FRDR = f32_mulAdd(FRS1, FRS2, FRS3) ^ (uint32_t)INT32_MIN;
 set_fp_exceptions;

riscv/insns/nmsub_d.h

@@ -1,3 +1,3 @@
 require_fp;
-FRC = f64_mulAdd(FRA, FRB, FRD ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN;
+FRDR = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN;
 set_fp_exceptions;

riscv/insns/nmsub_s.h

@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_mulAdd(FRA, FRB, FRD ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN;
+FRDR = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN;
 set_fp_exceptions;

riscv/insns/nor.h

@@ -1 +1 @@
-RC = ~(RA | RB);
+RDR = ~(RS1 | RS2);

riscv/insns/or.h

@@ -1 +1 @@
-RC = RA | RB;
+RDR = RS1 | RS2;

riscv/insns/ori.h

@@ -1 +1 @@
-RA = IMM | RB;
+RDI = IMM | RS1;

riscv/insns/rdnpc.h

@@ -1 +1 @@
-RC = npc;
+RDR = npc;

riscv/insns/rem.h

@@ -1,2 +1,2 @@
 require64;
-RC = sreg_t(RA) % sreg_t(RB);
+RDR = sreg_t(RS1) % sreg_t(RS2);

riscv/insns/remu.h

@@ -1,2 +1,2 @@
 require64;
-RC = RA % RB;
+RDR = RS1 % RS2;