Sv57 and Sv64 are not spec'd yet

riscv/encoding.h

@@ -106,26 +106,19 @@
 #define PRV_H 2
 #define PRV_M 3
 
-#define VM_MBARE 0
-#define VM_MBB   1
-#define VM_MBBID 2
-#define VM_SV32  8
-#define VM_SV39  9
-#define VM_SV48  10
-
 #define SPTBR32_MODE 0x80000000
 #define SPTBR32_ASID 0x7FC00000
 #define SPTBR32_PPN  0x003FFFFF
-#define SPTBR64_MODE 0xE000000000000000
-#define SPTBR64_ASID 0x1FFFE00000000000
-#define SPTBR64_PPN  0x0000003FFFFFFFFF
+#define SPTBR64_MODE 0xF000000000000000
+#define SPTBR64_ASID 0x0FFFF00000000000
+#define SPTBR64_PPN  0x00000FFFFFFFFFFF
 
 #define SPTBR_MODE_OFF  0
 #define SPTBR_MODE_SV32 1
-#define SPTBR_MODE_SV39 4
-#define SPTBR_MODE_SV48 5
-#define SPTBR_MODE_SV57 6
-#define SPTBR_MODE_SV64 7
+#define SPTBR_MODE_SV39 8
+#define SPTBR_MODE_SV48 9
+#define SPTBR_MODE_SV57 10
+#define SPTBR_MODE_SV64 11
 
 #define IRQ_S_SOFT   1
 #define IRQ_H_SOFT   2
@@ -167,10 +160,12 @@
 # define MSTATUS_SD MSTATUS64_SD
 # define SSTATUS_SD SSTATUS64_SD
 # define RISCV_PGLEVEL_BITS 9
+# define SPTBR_MODE SPTBR64_MODE
 #else
 # define MSTATUS_SD MSTATUS32_SD
 # define SSTATUS_SD SSTATUS32_SD
 # define RISCV_PGLEVEL_BITS 10
+# define SPTBR_MODE SPTBR32_MODE
 #endif
 #define RISCV_PGSHIFT 12
 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT)

riscv/processor.cc

@@ -367,7 +367,8 @@ void processor_t::set_csr(int which, reg_t val)
       if (max_xlen == 32)
         state.sptbr = val & (SPTBR32_PPN | SPTBR32_MODE);
       if (max_xlen == 64 && (get_field(val, SPTBR64_MODE) == SPTBR_MODE_OFF ||
-                             get_field(val, SPTBR64_MODE) >= SPTBR_MODE_SV39))
+                             get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV39 ||
+                             get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV48))
         state.sptbr = val & (SPTBR64_PPN | SPTBR64_MODE);
       break;
     }