Priv virtual memory updates (#750)

* Priv virtual memory updates

* Priv 1.12 requires page faults when the address translation process
reaches a PTE with any reserved bit set

* Svpbmt uses two PTE bits, but otherwise has no effect on Spike (since
Spike is sequentially consistent and does not model PMAs)

* Add Svinval instructions

Even though I updated riscv-opcodes separately, I merged the new
defines into riscv/encoding.h manually, because riscv-opcodes seems
to be a step ahead of riscv-isa-sim for a few vector opcodes, causing
conflicts when regenerating encoding.h...

If that gets fixed, and encoding.h gets regenerated automatically, I can
remove it from this PR to avoid conflicts.

* Svinval: use #include rather than copying code

..for the Svinval functions that are implemented in ways that just
mimic SFENCE/HFENCE instructions

Thanks to @aswaterman for the suggestion

README.md

@@ -27,6 +27,8 @@ Spike supports the following RISC-V ISA features:
   - Machine, Supervisor, and User modes, v1.11
   - Hypervisor extension, v0.6.1
   - Svnapot extension, v0.1
+  - Svpbmt extension, v0.1
+  - Svinval extension, v0.1
   - Debug v0.14
 
 Versioning and APIs

disasm/disasm.cc

@@ -662,6 +662,12 @@ disassembler_t::disassembler_t(int xlen)
   DEFINE_NOARG(fence_i);
   DEFINE_SFENCE_TYPE(sfence_vma);
 
+  DEFINE_NOARG(sfence_w_inval);
+  DEFINE_NOARG(sfence_inval_ir);
+  DEFINE_SFENCE_TYPE(sinval_vma);
+  DEFINE_SFENCE_TYPE(hinval_vvma);
+  DEFINE_SFENCE_TYPE(hinval_gvma);
+
   add_insn(new disasm_insn_t("csrr", match_csrrs, mask_csrrs | mask_rs1, {&xrd, &csr}));
   add_insn(new disasm_insn_t("csrw", match_csrrw, mask_csrrw | mask_rd, {&csr, &xrs1}));
   add_insn(new disasm_insn_t("csrs", match_csrrs, mask_csrrs | mask_rd, {&csr, &xrs1}));

riscv/encoding.h

@@ -221,7 +221,10 @@
 #define PTE_A     0x040 /* Accessed */
 #define PTE_D     0x080 /* Dirty */
 #define PTE_SOFT  0x300 /* Reserved for Software */
+#define PTE_RSVD  0x1FC0000000000000 /* Reserved for future standard use */
+#define PTE_PBMT  0x6000000000000000 /* Svpbmt: Page-based memory types */
 #define PTE_N     0x8000000000000000 /* Svnapot: NAPOT translation contiguity */
+#define PTE_ATTR  0xFFC0000000000000 /* All attributes and reserved bits */
 
 #define PTE_PPN_SHIFT 10
 
@@ -1020,6 +1023,16 @@
 #define MASK_CSRRSI  0x707f
 #define MATCH_CSRRCI 0x7073
 #define MASK_CSRRCI  0x707f
+#define MATCH_SINVAL_VMA 0x16000073
+#define MASK_SINVAL_VMA  0xfe007fff
+#define MATCH_SFENCE_W_INVAL 0x18000073
+#define MASK_SFENCE_W_INVAL  0xfff07fff
+#define MATCH_SFENCE_INVAL_IR 0x18100073
+#define MASK_SFENCE_INVAL_IR  0xfff07fff
+#define MATCH_HINVAL_VVMA 0x36000073
+#define MASK_HINVAL_VVMA  0xfe007fff
+#define MATCH_HINVAL_GVMA 0x76000073
+#define MASK_HINVAL_GVMA  0xfe007fff
 #define MATCH_FADD_H 0x4000053
 #define MASK_FADD_H  0xfe00007f
 #define MATCH_FSUB_H 0xc000053
@@ -3475,6 +3488,11 @@ DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
 DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
 DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
 DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
+DECLARE_INSN(sinval_vma, MATCH_SINVAL_VMA, MASK_SINVAL_VMA)
+DECLARE_INSN(sfence_w_inval, MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL)
+DECLARE_INSN(sfence_inval_ir, MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR)
+DECLARE_INSN(hinval_vvma, MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA)
+DECLARE_INSN(hinval_gvma, MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA)
 DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H)
 DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H)
 DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H)

riscv/insns/hinval_gvma.h

@@ -0,0 +1 @@
+#include "hfence_gvma.h"

riscv/insns/hinval_vvma.h

@@ -0,0 +1 @@
+#include "hfence_vvma.h"

riscv/insns/sfence_inval_ir.h

@@ -0,0 +1,2 @@
+require_extension('S');
+require_impl(IMPL_MMU);

riscv/insns/sfence_w_inval.h

@@ -0,0 +1,2 @@
+require_extension('S');
+require_impl(IMPL_MMU);

riscv/insns/sinval_vma.h

@@ -0,0 +1 @@
+#include "sfence_vma.h"

riscv/mmu.cc

@@ -328,9 +328,11 @@ reg_t mmu_t::s2xlate(reg_t gva, reg_t gpa, access_type type, access_type trap_ty
     }
 
     reg_t pte = vm.ptesize == 4 ? from_target(*(target_endian<uint32_t>*)ppte) : from_target(*(target_endian<uint64_t>*)ppte);
-    reg_t ppn = (pte & ~reg_t(PTE_N)) >> PTE_PPN_SHIFT;
+    reg_t ppn = (pte & ~reg_t(PTE_ATTR)) >> PTE_PPN_SHIFT;
 
-    if (PTE_TABLE(pte)) { // next level of page table
+    if (pte & PTE_RSVD) {
+      break;
+    } else if (PTE_TABLE(pte)) { // next level of page table
       base = ppn << PGSHIFT;
     } else if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) {
       break;
@@ -408,9 +410,11 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode, bool virt, bool mxr)
       throw_access_exception(virt, addr, type);
 
     reg_t pte = vm.ptesize == 4 ? from_target(*(target_endian<uint32_t>*)ppte) : from_target(*(target_endian<uint64_t>*)ppte);
-    reg_t ppn = (pte & ~reg_t(PTE_N)) >> PTE_PPN_SHIFT;
+    reg_t ppn = (pte & ~reg_t(PTE_ATTR)) >> PTE_PPN_SHIFT;
 
-    if (PTE_TABLE(pte)) { // next level of page table
+    if (pte & PTE_RSVD) {
+      break;
+    } else if (PTE_TABLE(pte)) { // next level of page table
       base = ppn << PGSHIFT;
     } else if ((pte & PTE_U) ? s_mode && (type == FETCH || !sum) : !s_mode) {
       break;

riscv/riscv.mk.in

@@ -1262,6 +1262,12 @@ riscv_insn_priv = \
 	sret \
 	wfi \
 
+riscv_insn_svinval = \
+	sfence_w_inval \
+	sfence_inval_ir \
+	sinval_vma \
+	hinval_vvma \
+	hinval_gvma \
 
 riscv_insn_list = \
 	$(riscv_insn_ext_a) \
@@ -1278,6 +1284,7 @@ riscv_insn_list = \
 	$(riscv_insn_ext_h) \
 	$(riscv_insn_ext_p) \
 	$(riscv_insn_priv) \
+	$(riscv_insn_svinval) \
 
 riscv_gen_srcs = \
 	$(addsuffix .cc,$(riscv_insn_list))