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riscv-isa-sim
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Update Zba/Zbb/Zbc to v0.93; Zbs/Zbe to v0.94-draft

pull/625/head
Andrew Waterman 6 years ago
parent
c14c1ab21e
commit
c9af3ebbcc
33 changed files with 395 additions and 463 deletions
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  1. 25
      disasm/disasm.cc
  2. 730
      riscv/encoding.h
  3. 0
      riscv/insns/add_uw.h
  4. 3
      riscv/insns/addiwu.h
  5. 3
      riscv/insns/addwu.h
  6. 0
      riscv/insns/bclr.h
  7. 0
      riscv/insns/bclri.h
  8. 9
      riscv/insns/bcompress.h
  9. 0
      riscv/insns/bcompressw.h
  10. 0
      riscv/insns/bdecompress.h
  11. 0
      riscv/insns/bdecompressw.h
  12. 10
      riscv/insns/bext.h
  13. 0
      riscv/insns/bexti.h
  14. 0
      riscv/insns/binv.h
  15. 0
      riscv/insns/binvi.h
  16. 0
      riscv/insns/bset.h
  17. 0
      riscv/insns/bseti.h
  18. 0
      riscv/insns/cpop.h
  19. 0
      riscv/insns/cpopw.h
  20. 3
      riscv/insns/sbclriw.h
  21. 3
      riscv/insns/sbclrw.h
  22. 3
      riscv/insns/sbext.h
  23. 3
      riscv/insns/sbextw.h
  24. 3
      riscv/insns/sbinviw.h
  25. 3
      riscv/insns/sbinvw.h
  26. 3
      riscv/insns/sbsetiw.h
  27. 3
      riscv/insns/sbsetw.h
  28. 0
      riscv/insns/sh1add_uw.h
  29. 0
      riscv/insns/sh2add_uw.h
  30. 0
      riscv/insns/sh3add_uw.h
  31. 0
      riscv/insns/slli_uw.h
  32. 3
      riscv/insns/subwu.h
  33. 51
      riscv/riscv.mk.in

25
disasm/disasm.cc
View File

@ -398,7 +398,7 @@ disassembler_t::disassembler_t(int xlen)
const uint32_t match_rs1_ra = 1UL << 15;
const uint32_t mask_rs2 = 0x1fUL << 20;
const uint32_t mask_imm = 0xfffUL << 20;
const uint32_t match_imm_1 = 1UL << 20;
const uint32_t imm_shift = 20;
const uint32_t mask_rvc_rs2 = 0x1fUL << 2;
const uint32_t mask_rvc_imm = mask_rvc_rs2 | 0x1000UL;
const uint32_t mask_nf = 0x7Ul << 29;
@ -519,7 +519,7 @@ disassembler_t::disassembler_t(int xlen)
DEFINE_I1TYPE("mv", addi);
DEFINE_ITYPE(addi);
DEFINE_ITYPE(slti);
add_insn(new disasm_insn_t("seqz", match_sltiu | match_imm_1, mask_sltiu | mask_imm, {&xrd, &xrs1}));
add_insn(new disasm_insn_t("seqz", match_sltiu | (1 << imm_shift), mask_sltiu | mask_imm, {&xrd, &xrs1}));
DEFINE_ITYPE(sltiu);
add_insn(new disasm_insn_t("not", match_xori | mask_imm, mask_xori | mask_imm, {&xrd, &xrs1}));
DEFINE_ITYPE(xori);
@ -567,17 +567,15 @@ disassembler_t::disassembler_t(int xlen)
DEFINE_RTYPE(remw);
DEFINE_RTYPE(remuw);
DEFINE_ITYPE_SHIFT(slliu_w);
DEFINE_RTYPE(addu_w);
DEFINE_ITYPE_SHIFT(slli_uw);
add_insn(new disasm_insn_t("zext.w", match_add_uw, mask_add_uw | mask_rs2, {&xrd, &xrs1}));
DEFINE_RTYPE(add_uw);
DEFINE_RTYPE(sh1add);
DEFINE_RTYPE(sh2add);
DEFINE_RTYPE(sh3add);
DEFINE_RTYPE(sh1addu_w);
DEFINE_RTYPE(sh2addu_w);
DEFINE_RTYPE(sh3addu_w);
DEFINE_RTYPE(addwu);
DEFINE_RTYPE(subwu);
DEFINE_ITYPE(addiwu);
DEFINE_RTYPE(sh1add_uw);
DEFINE_RTYPE(sh2add_uw);
DEFINE_RTYPE(sh3add_uw);
DEFINE_RTYPE(ror);
DEFINE_RTYPE(rorw);
DEFINE_RTYPE(rol);
@ -588,8 +586,8 @@ disassembler_t::disassembler_t(int xlen)
DEFINE_R1TYPE(ctzw);
DEFINE_R1TYPE(clz);
DEFINE_R1TYPE(clzw);
DEFINE_R1TYPE(pcnt);
DEFINE_R1TYPE(pcntw);
DEFINE_R1TYPE(cpop);
DEFINE_R1TYPE(cpopw);
DEFINE_RTYPE(min);
DEFINE_RTYPE(minu);
DEFINE_RTYPE(max);
@ -599,11 +597,14 @@ disassembler_t::disassembler_t(int xlen)
DEFINE_RTYPE(xnor);
DEFINE_R1TYPE(sext_b);
DEFINE_R1TYPE(sext_h);
add_insn(new disasm_insn_t("zext.h", (xlen == 32 ? match_pack : match_packw), mask_pack | mask_rs2, {&xrd, &xrs1}));
DEFINE_RTYPE(pack);
DEFINE_RTYPE(packw);
DEFINE_RTYPE(grev);
add_insn(new disasm_insn_t("rev8", match_grevi | ((xlen == 32 ? 0x18 : 0x38) << imm_shift), mask_grevi | mask_imm, {&xrd, &xrs1}));
DEFINE_ITYPE_SHIFT(grevi);
DEFINE_RTYPE(gorc);
add_insn(new disasm_insn_t("orc.b", match_gorci | (0x7 << imm_shift), mask_grevi | mask_imm, {&xrd, &xrs1}));
DEFINE_ITYPE_SHIFT(gorci);
DEFINE_NOARG(ecall);

730
riscv/encoding.h
View File

@ -1,3 +1,8 @@
/*
* This file is auto-generated by running 'make ../riscv-isa-sim/riscv/encoding.h' in
* https://github.com/riscv/riscv-opcodes (2aa7492)
*/
/* See LICENSE for license details. */
#ifndef RISCV_CSR_ENCODING_H
@ -455,218 +460,6 @@
#define MASK_REMW 0xfe00707f
#define MATCH_REMUW 0x200703b
#define MASK_REMUW 0xfe00707f
#define MATCH_ANDN 0x40007033
#define MASK_ANDN 0xfe00707f
#define MATCH_ORN 0x40006033
#define MASK_ORN 0xfe00707f
#define MATCH_XNOR 0x40004033
#define MASK_XNOR 0xfe00707f
#define MATCH_SLO 0x20001033
#define MASK_SLO 0xfe00707f
#define MATCH_SRO 0x20005033
#define MASK_SRO 0xfe00707f
#define MATCH_ROL 0x60001033
#define MASK_ROL 0xfe00707f
#define MATCH_ROR 0x60005033
#define MASK_ROR 0xfe00707f
#define MATCH_SBCLR 0x48001033
#define MASK_SBCLR 0xfe00707f
#define MATCH_SBSET 0x28001033
#define MASK_SBSET 0xfe00707f
#define MATCH_SBINV 0x68001033
#define MASK_SBINV 0xfe00707f
#define MATCH_SBEXT 0x48005033
#define MASK_SBEXT 0xfe00707f
#define MATCH_GORC 0x28005033
#define MASK_GORC 0xfe00707f
#define MATCH_GREV 0x68005033
#define MASK_GREV 0xfe00707f
#define MATCH_SLOI 0x20001013
#define MASK_SLOI 0xfc00707f
#define MATCH_SROI 0x20005013
#define MASK_SROI 0xfc00707f
#define MATCH_RORI 0x60005013
#define MASK_RORI 0xfc00707f
#define MATCH_SBCLRI 0x48001013
#define MASK_SBCLRI 0xfc00707f
#define MATCH_SBSETI 0x28001013
#define MASK_SBSETI 0xfc00707f
#define MATCH_SBINVI 0x68001013
#define MASK_SBINVI 0xfc00707f
#define MATCH_SBEXTI 0x48005013
#define MASK_SBEXTI 0xfc00707f
#define MATCH_GORCI 0x28005013
#define MASK_GORCI 0xfc00707f
#define MATCH_GREVI 0x68005013
#define MASK_GREVI 0xfc00707f
#define MATCH_CMIX 0x6001033
#define MASK_CMIX 0x600707f
#define MATCH_CMOV 0x6005033
#define MASK_CMOV 0x600707f
#define MATCH_FSL 0x4001033
#define MASK_FSL 0x600707f
#define MATCH_FSR 0x4005033
#define MASK_FSR 0x600707f
#define MATCH_FSRI 0x4005013
#define MASK_FSRI 0x400707f
#define MATCH_CLZ 0x60001013
#define MASK_CLZ 0xfff0707f
#define MATCH_CTZ 0x60101013
#define MASK_CTZ 0xfff0707f
#define MATCH_PCNT 0x60201013
#define MASK_PCNT 0xfff0707f
#define MATCH_SEXT_B 0x60401013
#define MASK_SEXT_B 0xfff0707f
#define MATCH_SEXT_H 0x60501013
#define MASK_SEXT_H 0xfff0707f
#define MATCH_CRC32_B 0x61001013
#define MASK_CRC32_B 0xfff0707f
#define MATCH_CRC32_H 0x61101013
#define MASK_CRC32_H 0xfff0707f
#define MATCH_CRC32_W 0x61201013
#define MASK_CRC32_W 0xfff0707f
#define MATCH_CRC32C_B 0x61801013
#define MASK_CRC32C_B 0xfff0707f
#define MATCH_CRC32C_H 0x61901013
#define MASK_CRC32C_H 0xfff0707f
#define MATCH_CRC32C_W 0x61a01013
#define MASK_CRC32C_W 0xfff0707f
#define MATCH_SH1ADD 0x20002033
#define MASK_SH1ADD 0xfe00707f
#define MATCH_SH2ADD 0x20004033
#define MASK_SH2ADD 0xfe00707f
#define MATCH_SH3ADD 0x20006033
#define MASK_SH3ADD 0xfe00707f
#define MATCH_CLMUL 0xa001033
#define MASK_CLMUL 0xfe00707f
#define MATCH_CLMULR 0xa002033
#define MASK_CLMULR 0xfe00707f
#define MATCH_CLMULH 0xa003033
#define MASK_CLMULH 0xfe00707f
#define MATCH_MIN 0xa004033
#define MASK_MIN 0xfe00707f
#define MATCH_MINU 0xa005033
#define MASK_MINU 0xfe00707f
#define MATCH_MAX 0xa006033
#define MASK_MAX 0xfe00707f
#define MATCH_MAXU 0xa007033
#define MASK_MAXU 0xfe00707f
#define MATCH_SHFL 0x8001033
#define MASK_SHFL 0xfe00707f
#define MATCH_UNSHFL 0x8005033
#define MASK_UNSHFL 0xfe00707f
#define MATCH_BEXT 0x8006033
#define MASK_BEXT 0xfe00707f
#define MATCH_BDEP 0x48006033
#define MASK_BDEP 0xfe00707f
#define MATCH_PACK 0x8004033
#define MASK_PACK 0xfe00707f
#define MATCH_PACKU 0x48004033
#define MASK_PACKU 0xfe00707f
#define MATCH_PACKH 0x8007033
#define MASK_PACKH 0xfe00707f
#define MATCH_BFP 0x48007033
#define MASK_BFP 0xfe00707f
#define MATCH_SHFLI 0x8001013
#define MASK_SHFLI 0xfe00707f
#define MATCH_UNSHFLI 0x8005013
#define MASK_UNSHFLI 0xfe00707f
#define MATCH_BMATFLIP 0x60301013
#define MASK_BMATFLIP 0xfff0707f
#define MATCH_CRC32_D 0x61301013
#define MASK_CRC32_D 0xfff0707f
#define MATCH_CRC32C_D 0x61b01013
#define MASK_CRC32C_D 0xfff0707f
#define MATCH_BMATOR 0x8003033
#define MASK_BMATOR 0xfe00707f
#define MATCH_BMATXOR 0x48003033
#define MASK_BMATXOR 0xfe00707f
#define MATCH_ADDIWU 0x401b
#define MASK_ADDIWU 0x707f
#define MATCH_SLLIU_W 0x800101b
#define MASK_SLLIU_W 0xfc00707f
#define MATCH_ADDWU 0xa00003b
#define MASK_ADDWU 0xfe00707f
#define MATCH_SUBWU 0x4a00003b
#define MASK_SUBWU 0xfe00707f
#define MATCH_ADDU_W 0x800003b
#define MASK_ADDU_W 0xfe00707f
#define MATCH_SUBU_W 0x4800003b
#define MASK_SUBU_W 0xfe00707f
#define MATCH_SLOW 0x2000103b
#define MASK_SLOW 0xfe00707f
#define MATCH_SROW 0x2000503b
#define MASK_SROW 0xfe00707f
#define MATCH_ROLW 0x6000103b
#define MASK_ROLW 0xfe00707f
#define MATCH_RORW 0x6000503b
#define MASK_RORW 0xfe00707f
#define MATCH_SBCLRW 0x4800103b
#define MASK_SBCLRW 0xfe00707f
#define MATCH_SBSETW 0x2800103b
#define MASK_SBSETW 0xfe00707f
#define MATCH_SBINVW 0x6800103b
#define MASK_SBINVW 0xfe00707f
#define MATCH_SBEXTW 0x4800503b
#define MASK_SBEXTW 0xfe00707f
#define MATCH_GORCW 0x2800503b
#define MASK_GORCW 0xfe00707f
#define MATCH_GREVW 0x6800503b
#define MASK_GREVW 0xfe00707f
#define MATCH_SLOIW 0x2000101b
#define MASK_SLOIW 0xfe00707f
#define MATCH_SROIW 0x2000501b
#define MASK_SROIW 0xfe00707f
#define MATCH_RORIW 0x6000501b
#define MASK_RORIW 0xfe00707f
#define MATCH_SBCLRIW 0x4800101b
#define MASK_SBCLRIW 0xfe00707f
#define MATCH_SBSETIW 0x2800101b
#define MASK_SBSETIW 0xfe00707f
#define MATCH_SBINVIW 0x6800101b
#define MASK_SBINVIW 0xfe00707f
#define MATCH_GORCIW 0x2800501b
#define MASK_GORCIW 0xfe00707f
#define MATCH_GREVIW 0x6800501b
#define MASK_GREVIW 0xfe00707f
#define MATCH_FSLW 0x400103b
#define MASK_FSLW 0x600707f
#define MATCH_FSRW 0x400503b
#define MASK_FSRW 0x600707f
#define MATCH_FSRIW 0x400501b
#define MASK_FSRIW 0x600707f
#define MATCH_CLZW 0x6000101b
#define MASK_CLZW 0xfff0707f
#define MATCH_CTZW 0x6010101b
#define MASK_CTZW 0xfff0707f
#define MATCH_PCNTW 0x6020101b
#define MASK_PCNTW 0xfff0707f
#define MATCH_SH1ADDU_W 0x2000203b
#define MASK_SH1ADDU_W 0xfe00707f
#define MATCH_SH2ADDU_W 0x2000403b
#define MASK_SH2ADDU_W 0xfe00707f
#define MATCH_SH3ADDU_W 0x2000603b
#define MASK_SH3ADDU_W 0xfe00707f
#define MATCH_CLMULW 0xa00103b
#define MASK_CLMULW 0xfe00707f
#define MATCH_CLMULRW 0xa00203b
#define MASK_CLMULRW 0xfe00707f
#define MATCH_CLMULHW 0xa00303b
#define MASK_CLMULHW 0xfe00707f
#define MATCH_SHFLW 0x800103b
#define MASK_SHFLW 0xfe00707f
#define MATCH_UNSHFLW 0x800503b
#define MASK_UNSHFLW 0xfe00707f
#define MATCH_BEXTW 0x800603b
#define MASK_BEXTW 0xfe00707f
#define MATCH_BDEPW 0x4800603b
#define MASK_BDEPW 0xfe00707f
#define MATCH_PACKW 0x800403b
#define MASK_PACKW 0xfe00707f
#define MATCH_PACKUW 0x4800403b
#define MASK_PACKUW 0xfe00707f
#define MATCH_BFPW 0x4800703b
#define MASK_BFPW 0xfe00707f
#define MATCH_AMOADD_W 0x202f
#define MASK_AMOADD_W 0xf800707f
#define MATCH_AMOXOR_W 0x2000202f
@ -929,10 +722,232 @@
#define MASK_FCVT_Q_L 0xfff0007f
#define MATCH_FCVT_Q_LU 0xd6300053
#define MASK_FCVT_Q_LU 0xfff0007f
#define MATCH_FMV_X_Q 0xe6000053
#define MASK_FMV_X_Q 0xfff0707f
#define MATCH_FMV_Q_X 0xf6000053
#define MASK_FMV_Q_X 0xfff0707f
#define MATCH_ANDN 0x40007033
#define MASK_ANDN 0xfe00707f
#define MATCH_ORN 0x40006033
#define MASK_ORN 0xfe00707f
#define MATCH_XNOR 0x40004033
#define MASK_XNOR 0xfe00707f
#define MATCH_SLO 0x20001033
#define MASK_SLO 0xfe00707f
#define MATCH_SRO 0x20005033
#define MASK_SRO 0xfe00707f
#define MATCH_ROL 0x60001033
#define MASK_ROL 0xfe00707f
#define MATCH_ROR 0x60005033
#define MASK_ROR 0xfe00707f
#define MATCH_BCLR 0x48001033
#define MASK_BCLR 0xfe00707f
#define MATCH_BSET 0x28001033
#define MASK_BSET 0xfe00707f
#define MATCH_BINV 0x68001033
#define MASK_BINV 0xfe00707f
#define MATCH_BEXT 0x48005033
#define MASK_BEXT 0xfe00707f
#define MATCH_GORC 0x28005033
#define MASK_GORC 0xfe00707f
#define MATCH_GREV 0x68005033
#define MASK_GREV 0xfe00707f
#define MATCH_SLOI 0x20001013
#define MASK_SLOI 0xfc00707f
#define MATCH_SROI 0x20005013
#define MASK_SROI 0xfc00707f
#define MATCH_RORI 0x60005013
#define MASK_RORI 0xfc00707f
#define MATCH_BCLRI 0x48001013
#define MASK_BCLRI 0xfc00707f
#define MATCH_BSETI 0x28001013
#define MASK_BSETI 0xfc00707f
#define MATCH_BINVI 0x68001013
#define MASK_BINVI 0xfc00707f
#define MATCH_BEXTI 0x48005013
#define MASK_BEXTI 0xfc00707f
#define MATCH_GORCI 0x28005013
#define MASK_GORCI 0xfc00707f
#define MATCH_GREVI 0x68005013
#define MASK_GREVI 0xfc00707f
#define MATCH_CMIX 0x6001033
#define MASK_CMIX 0x600707f
#define MATCH_CMOV 0x6005033
#define MASK_CMOV 0x600707f
#define MATCH_FSL 0x4001033
#define MASK_FSL 0x600707f
#define MATCH_FSR 0x4005033
#define MASK_FSR 0x600707f
#define MATCH_FSRI 0x4005013
#define MASK_FSRI 0x400707f
#define MATCH_CLZ 0x60001013
#define MASK_CLZ 0xfff0707f
#define MATCH_CTZ 0x60101013
#define MASK_CTZ 0xfff0707f
#define MATCH_CPOP 0x60201013
#define MASK_CPOP 0xfff0707f
#define MATCH_SEXT_B 0x60401013
#define MASK_SEXT_B 0xfff0707f
#define MATCH_SEXT_H 0x60501013
#define MASK_SEXT_H 0xfff0707f
#define MATCH_CRC32_B 0x61001013
#define MASK_CRC32_B 0xfff0707f
#define MATCH_CRC32_H 0x61101013
#define MASK_CRC32_H 0xfff0707f
#define MATCH_CRC32_W 0x61201013
#define MASK_CRC32_W 0xfff0707f
#define MATCH_CRC32C_B 0x61801013
#define MASK_CRC32C_B 0xfff0707f
#define MATCH_CRC32C_H 0x61901013
#define MASK_CRC32C_H 0xfff0707f
#define MATCH_CRC32C_W 0x61a01013
#define MASK_CRC32C_W 0xfff0707f
#define MATCH_SH1ADD 0x20002033
#define MASK_SH1ADD 0xfe00707f
#define MATCH_SH2ADD 0x20004033
#define MASK_SH2ADD 0xfe00707f
#define MATCH_SH3ADD 0x20006033
#define MASK_SH3ADD 0xfe00707f
#define MATCH_CLMUL 0xa001033
#define MASK_CLMUL 0xfe00707f
#define MATCH_CLMULR 0xa002033
#define MASK_CLMULR 0xfe00707f
#define MATCH_CLMULH 0xa003033
#define MASK_CLMULH 0xfe00707f
#define MATCH_MIN 0xa004033
#define MASK_MIN 0xfe00707f
#define MATCH_MINU 0xa005033
#define MASK_MINU 0xfe00707f
#define MATCH_MAX 0xa006033
#define MASK_MAX 0xfe00707f
#define MATCH_MAXU 0xa007033
#define MASK_MAXU 0xfe00707f
#define MATCH_SHFL 0x8001033
#define MASK_SHFL 0xfe00707f
#define MATCH_UNSHFL 0x8005033
#define MASK_UNSHFL 0xfe00707f
#define MATCH_BCOMPRESS 0x8006033
#define MASK_BCOMPRESS 0xfe00707f
#define MATCH_BDECOMPRESS 0x48006033
#define MASK_BDECOMPRESS 0xfe00707f
#define MATCH_PACK 0x8004033
#define MASK_PACK 0xfe00707f
#define MATCH_PACKU 0x48004033
#define MASK_PACKU 0xfe00707f
#define MATCH_PACKH 0x8007033
#define MASK_PACKH 0xfe00707f
#define MATCH_BFP 0x48007033
#define MASK_BFP 0xfe00707f
#define MATCH_SHFLI 0x8001013
#define MASK_SHFLI 0xfe00707f
#define MATCH_UNSHFLI 0x8005013
#define MASK_UNSHFLI 0xfe00707f
#define MATCH_BMATFLIP 0x60301013
#define MASK_BMATFLIP 0xfff0707f
#define MATCH_CRC32_D 0x61301013
#define MASK_CRC32_D 0xfff0707f
#define MATCH_CRC32C_D 0x61b01013
#define MASK_CRC32C_D 0xfff0707f
#define MATCH_BMATOR 0x8003033
#define MASK_BMATOR 0xfe00707f
#define MATCH_BMATXOR 0x48003033
#define MASK_BMATXOR 0xfe00707f
#define MATCH_SLLI_UW 0x800101b
#define MASK_SLLI_UW 0xfc00707f
#define MATCH_ADD_UW 0x800003b
#define MASK_ADD_UW 0xfe00707f
#define MATCH_SLOW 0x2000103b
#define MASK_SLOW 0xfe00707f
#define MATCH_SROW 0x2000503b
#define MASK_SROW 0xfe00707f
#define MATCH_ROLW 0x6000103b
#define MASK_ROLW 0xfe00707f
#define MATCH_RORW 0x6000503b
#define MASK_RORW 0xfe00707f
#define MATCH_SBCLRW 0x4800103b
#define MASK_SBCLRW 0xfe00707f
#define MATCH_SBSETW 0x2800103b
#define MASK_SBSETW 0xfe00707f
#define MATCH_SBINVW 0x6800103b
#define MASK_SBINVW 0xfe00707f
#define MATCH_SBEXTW 0x4800503b
#define MASK_SBEXTW 0xfe00707f
#define MATCH_GORCW 0x2800503b
#define MASK_GORCW 0xfe00707f
#define MATCH_GREVW 0x6800503b
#define MASK_GREVW 0xfe00707f
#define MATCH_SLOIW 0x2000101b
#define MASK_SLOIW 0xfe00707f
#define MATCH_SROIW 0x2000501b
#define MASK_SROIW 0xfe00707f
#define MATCH_RORIW 0x6000501b
#define MASK_RORIW 0xfe00707f
#define MATCH_SBCLRIW 0x4800101b
#define MASK_SBCLRIW 0xfe00707f
#define MATCH_SBSETIW 0x2800101b
#define MASK_SBSETIW 0xfe00707f
#define MATCH_SBINVIW 0x6800101b
#define MASK_SBINVIW 0xfe00707f
#define MATCH_GORCIW 0x2800501b
#define MASK_GORCIW 0xfe00707f
#define MATCH_GREVIW 0x6800501b
#define MASK_GREVIW 0xfe00707f
#define MATCH_FSLW 0x400103b
#define MASK_FSLW 0x600707f
#define MATCH_FSRW 0x400503b
#define MASK_FSRW 0x600707f
#define MATCH_FSRIW 0x400501b
#define MASK_FSRIW 0x600707f
#define MATCH_CLZW 0x6000101b
#define MASK_CLZW 0xfff0707f
#define MATCH_CTZW 0x6010101b
#define MASK_CTZW 0xfff0707f
#define MATCH_CPOPW 0x6020101b
#define MASK_CPOPW 0xfff0707f
#define MATCH_SH1ADD_UW 0x2000203b
#define MASK_SH1ADD_UW 0xfe00707f
#define MATCH_SH2ADD_UW 0x2000403b
#define MASK_SH2ADD_UW 0xfe00707f
#define MATCH_SH3ADD_UW 0x2000603b
#define MASK_SH3ADD_UW 0xfe00707f
#define MATCH_SHFLW 0x800103b
#define MASK_SHFLW 0xfe00707f
#define MATCH_UNSHFLW 0x800503b
#define MASK_UNSHFLW 0xfe00707f
#define MATCH_BCOMPRESSW 0x800603b
#define MASK_BCOMPRESSW 0xfe00707f
#define MATCH_BDECOMPRESSW 0x4800603b
#define MASK_BDECOMPRESSW 0xfe00707f
#define MATCH_PACKW 0x800403b
#define MASK_PACKW 0xfe00707f
#define MATCH_PACKUW 0x4800403b
#define MASK_PACKUW 0xfe00707f
#define MATCH_BFPW 0x4800703b
#define MASK_BFPW 0xfe00707f
#define MATCH_ECALL 0x73
#define MASK_ECALL 0xffffffff
#define MATCH_EBREAK 0x100073
#define MASK_EBREAK 0xffffffff
#define MATCH_URET 0x200073
#define MASK_URET 0xffffffff
#define MATCH_SRET 0x10200073
#define MASK_SRET 0xffffffff
#define MATCH_MRET 0x30200073
#define MASK_MRET 0xffffffff
#define MATCH_DRET 0x7b200073
#define MASK_DRET 0xffffffff
#define MATCH_SFENCE_VMA 0x12000073
#define MASK_SFENCE_VMA 0xfe007fff
#define MATCH_WFI 0x10500073
#define MASK_WFI 0xffffffff
#define MATCH_CSRRW 0x1073
#define MASK_CSRRW 0x707f
#define MATCH_CSRRS 0x2073
#define MASK_CSRRS 0x707f
#define MATCH_CSRRC 0x3073
#define MASK_CSRRC 0x707f
#define MATCH_CSRRWI 0x5073
#define MASK_CSRRWI 0x707f
#define MATCH_CSRRSI 0x6073
#define MASK_CSRRSI 0x707f
#define MATCH_CSRRCI 0x7073
#define MASK_CSRRCI 0x707f
#define MATCH_FADD_H 0x4000053
#define MASK_FADD_H 0xfe00007f
#define MATCH_FSUB_H 0xc000053
@ -1005,34 +1020,6 @@
#define MASK_FCVT_H_L 0xfff0007f
#define MATCH_FCVT_H_LU 0xd4300053
#define MASK_FCVT_H_LU 0xfff0007f
#define MATCH_ECALL 0x73
#define MASK_ECALL 0xffffffff
#define MATCH_EBREAK 0x100073
#define MASK_EBREAK 0xffffffff
#define MATCH_URET 0x200073
#define MASK_URET 0xffffffff
#define MATCH_SRET 0x10200073
#define MASK_SRET 0xffffffff
#define MATCH_MRET 0x30200073
#define MASK_MRET 0xffffffff
#define MATCH_DRET 0x7b200073
#define MASK_DRET 0xffffffff
#define MATCH_SFENCE_VMA 0x12000073
#define MASK_SFENCE_VMA 0xfe007fff
#define MATCH_WFI 0x10500073
#define MASK_WFI 0xffffffff
#define MATCH_CSRRW 0x1073
#define MASK_CSRRW 0x707f
#define MATCH_CSRRS 0x2073
#define MASK_CSRRS 0x707f
#define MATCH_CSRRC 0x3073
#define MASK_CSRRC 0x707f
#define MATCH_CSRRWI 0x5073
#define MASK_CSRRWI 0x707f
#define MATCH_CSRRSI 0x6073
#define MASK_CSRRSI 0x707f
#define MATCH_CSRRCI 0x7073
#define MASK_CSRRCI 0x707f
#define MATCH_C_NOP 0x1
#define MASK_C_NOP 0xffff
#define MATCH_C_ADDI16SP 0x6101
@ -1123,14 +1110,6 @@
#define MASK_C_LDSP 0xe003
#define MATCH_C_SDSP 0xe002
#define MASK_C_SDSP 0xe003
#define MATCH_C_LQ 0x2000
#define MASK_C_LQ 0xe003
#define MATCH_C_SQ 0xa000
#define MASK_C_SQ 0xe003
#define MATCH_C_LQSP 0x2002
#define MASK_C_LQSP 0xe003
#define MATCH_C_SQSP 0xa002
#define MASK_C_SQSP 0xe003
#define MATCH_CUSTOM0 0xb
#define MASK_CUSTOM0 0x707f
#define MATCH_CUSTOM0_RS1 0x200b
@ -2217,6 +2196,10 @@
#define CSR_TDATA1 0x7a1
#define CSR_TDATA2 0x7a2
#define CSR_TDATA3 0x7a3
#define CSR_TINFO 0x7a4
#define CSR_TCONTROL 0x7a5
#define CSR_MCONTEXT 0x7a8
#define CSR_SCONTEXT 0x7aa
#define CSR_DCSR 0x7b0
#define CSR_DPC 0x7b1
#define CSR_DSCRATCH0 0x7b2
@ -2458,112 +2441,6 @@ DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN)
DECLARE_INSN(orn, MATCH_ORN, MASK_ORN)
DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR)
DECLARE_INSN(slo, MATCH_SLO, MASK_SLO)
DECLARE_INSN(sro, MATCH_SRO, MASK_SRO)
DECLARE_INSN(rol, MATCH_ROL, MASK_ROL)
DECLARE_INSN(ror, MATCH_ROR, MASK_ROR)
DECLARE_INSN(sbclr, MATCH_SBCLR, MASK_SBCLR)
DECLARE_INSN(sbset, MATCH_SBSET, MASK_SBSET)
DECLARE_INSN(sbinv, MATCH_SBINV, MASK_SBINV)
DECLARE_INSN(sbext, MATCH_SBEXT, MASK_SBEXT)
DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC)
DECLARE_INSN(grev, MATCH_GREV, MASK_GREV)
DECLARE_INSN(sloi, MATCH_SLOI, MASK_SLOI)
DECLARE_INSN(sroi, MATCH_SROI, MASK_SROI)
DECLARE_INSN(rori, MATCH_RORI, MASK_RORI)
DECLARE_INSN(sbclri, MATCH_SBCLRI, MASK_SBCLRI)
DECLARE_INSN(sbseti, MATCH_SBSETI, MASK_SBSETI)
DECLARE_INSN(sbinvi, MATCH_SBINVI, MASK_SBINVI)
DECLARE_INSN(sbexti, MATCH_SBEXTI, MASK_SBEXTI)
DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI)
DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI)
DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX)
DECLARE_INSN(cmov, MATCH_CMOV, MASK_CMOV)
DECLARE_INSN(fsl, MATCH_FSL, MASK_FSL)
DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR)
DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI)
DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ)
DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ)
DECLARE_INSN(pcnt, MATCH_PCNT, MASK_PCNT)
DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B)
DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H)
DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B)
DECLARE_INSN(crc32_h, MATCH_CRC32_H, MASK_CRC32_H)
DECLARE_INSN(crc32_w, MATCH_CRC32_W, MASK_CRC32_W)
DECLARE_INSN(crc32c_b, MATCH_CRC32C_B, MASK_CRC32C_B)
DECLARE_INSN(crc32c_h, MATCH_CRC32C_H, MASK_CRC32C_H)
DECLARE_INSN(crc32c_w, MATCH_CRC32C_W, MASK_CRC32C_W)
DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD)
DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD)
DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD)
DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
DECLARE_INSN(min, MATCH_MIN, MASK_MIN)
DECLARE_INSN(max, MATCH_MAX, MASK_MAX)
DECLARE_INSN(minu, MATCH_MINU, MASK_MINU)
DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU)
DECLARE_INSN(shfl, MATCH_SHFL, MASK_SHFL)
DECLARE_INSN(unshfl, MATCH_UNSHFL, MASK_UNSHFL)
DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT)
DECLARE_INSN(bdep, MATCH_BDEP, MASK_BDEP)
DECLARE_INSN(pack, MATCH_PACK, MASK_PACK)
DECLARE_INSN(packu, MATCH_PACKU, MASK_PACKU)
DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH)
DECLARE_INSN(bfp, MATCH_BFP, MASK_BFP)
DECLARE_INSN(shfli, MATCH_SHFLI, MASK_SHFLI)
DECLARE_INSN(unshfli, MATCH_UNSHFLI, MASK_UNSHFLI)
DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP)
DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D)
DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D)
DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR)
DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR)
DECLARE_INSN(addiwu, MATCH_ADDIWU, MASK_ADDIWU)
DECLARE_INSN(slliu_w, MATCH_SLLIU_W, MASK_SLLIU_W)
DECLARE_INSN(addwu, MATCH_ADDWU, MASK_ADDWU)
DECLARE_INSN(subwu, MATCH_SUBWU, MASK_SUBWU)
DECLARE_INSN(addu_w, MATCH_ADDU_W, MASK_ADDU_W)
DECLARE_INSN(subu_w, MATCH_SUBU_W, MASK_SUBU_W)
DECLARE_INSN(slow, MATCH_SLOW, MASK_SLOW)
DECLARE_INSN(srow, MATCH_SROW, MASK_SROW)
DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW)
DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW)
DECLARE_INSN(sbclrw, MATCH_SBCLRW, MASK_SBCLRW)
DECLARE_INSN(sbsetw, MATCH_SBSETW, MASK_SBSETW)
DECLARE_INSN(sbinvw, MATCH_SBINVW, MASK_SBINVW)
DECLARE_INSN(sbextw, MATCH_SBEXTW, MASK_SBEXTW)
DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW)
DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW)
DECLARE_INSN(sloiw, MATCH_SLOIW, MASK_SLOIW)
DECLARE_INSN(sroiw, MATCH_SROIW, MASK_SROIW)
DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW)
DECLARE_INSN(sbclriw, MATCH_SBCLRIW, MASK_SBCLRIW)
DECLARE_INSN(sbsetiw, MATCH_SBSETIW, MASK_SBSETIW)
DECLARE_INSN(sbinviw, MATCH_SBINVIW, MASK_SBINVIW)
DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW)
DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW)
DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW)
DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW)
DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW)
DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW)
DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW)
DECLARE_INSN(pcntw, MATCH_PCNTW, MASK_PCNTW)
DECLARE_INSN(sh1addu_w, MATCH_SH1ADDU_W, MASK_SH1ADDU_W)
DECLARE_INSN(sh2addu_w, MATCH_SH2ADDU_W, MASK_SH2ADDU_W)
DECLARE_INSN(sh3addu_w, MATCH_SH3ADDU_W, MASK_SH3ADDU_W)
DECLARE_INSN(clmulw, MATCH_CLMULW, MASK_CLMULW)
DECLARE_INSN(clmulrw, MATCH_CLMULRW, MASK_CLMULRW)
DECLARE_INSN(clmulhw, MATCH_CLMULHW, MASK_CLMULHW)
DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW)
DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW)
DECLARE_INSN(bextw, MATCH_BEXTW, MASK_BEXTW)
DECLARE_INSN(bdepw, MATCH_BDEPW, MASK_BDEPW)
DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW)
DECLARE_INSN(packuw, MATCH_PACKUW, MASK_PACKUW)
DECLARE_INSN(bfpw, MATCH_BFPW, MASK_BFPW)
DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
@ -2695,8 +2572,119 @@ DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)
DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q)
DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q)
DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN)
DECLARE_INSN(orn, MATCH_ORN, MASK_ORN)
DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR)
DECLARE_INSN(slo, MATCH_SLO, MASK_SLO)
DECLARE_INSN(sro, MATCH_SRO, MASK_SRO)
DECLARE_INSN(rol, MATCH_ROL, MASK_ROL)
DECLARE_INSN(ror, MATCH_ROR, MASK_ROR)
DECLARE_INSN(bclr, MATCH_BCLR, MASK_BCLR)
DECLARE_INSN(bset, MATCH_BSET, MASK_BSET)
DECLARE_INSN(binv, MATCH_BINV, MASK_BINV)
DECLARE_INSN(bext, MATCH_BEXT, MASK_BEXT)
DECLARE_INSN(gorc, MATCH_GORC, MASK_GORC)
DECLARE_INSN(grev, MATCH_GREV, MASK_GREV)
DECLARE_INSN(sloi, MATCH_SLOI, MASK_SLOI)
DECLARE_INSN(sroi, MATCH_SROI, MASK_SROI)
DECLARE_INSN(rori, MATCH_RORI, MASK_RORI)
DECLARE_INSN(bclri, MATCH_BCLRI, MASK_BCLRI)
DECLARE_INSN(bseti, MATCH_BSETI, MASK_BSETI)
DECLARE_INSN(binvi, MATCH_BINVI, MASK_BINVI)
DECLARE_INSN(bexti, MATCH_BEXTI, MASK_BEXTI)
DECLARE_INSN(gorci, MATCH_GORCI, MASK_GORCI)
DECLARE_INSN(grevi, MATCH_GREVI, MASK_GREVI)
DECLARE_INSN(cmix, MATCH_CMIX, MASK_CMIX)
DECLARE_INSN(cmov, MATCH_CMOV, MASK_CMOV)
DECLARE_INSN(fsl, MATCH_FSL, MASK_FSL)
DECLARE_INSN(fsr, MATCH_FSR, MASK_FSR)
DECLARE_INSN(fsri, MATCH_FSRI, MASK_FSRI)
DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ)
DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ)
DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP)
DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B)
DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H)
DECLARE_INSN(crc32_b, MATCH_CRC32_B, MASK_CRC32_B)
DECLARE_INSN(crc32_h, MATCH_CRC32_H, MASK_CRC32_H)
DECLARE_INSN(crc32_w, MATCH_CRC32_W, MASK_CRC32_W)
DECLARE_INSN(crc32c_b, MATCH_CRC32C_B, MASK_CRC32C_B)
DECLARE_INSN(crc32c_h, MATCH_CRC32C_H, MASK_CRC32C_H)
DECLARE_INSN(crc32c_w, MATCH_CRC32C_W, MASK_CRC32C_W)
DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD)
DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD)
DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD)
DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
DECLARE_INSN(min, MATCH_MIN, MASK_MIN)
DECLARE_INSN(minu, MATCH_MINU, MASK_MINU)
DECLARE_INSN(max, MATCH_MAX, MASK_MAX)
DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU)
DECLARE_INSN(shfl, MATCH_SHFL, MASK_SHFL)
DECLARE_INSN(unshfl, MATCH_UNSHFL, MASK_UNSHFL)
DECLARE_INSN(bcompress, MATCH_BCOMPRESS, MASK_BCOMPRESS)
DECLARE_INSN(bdecompress, MATCH_BDECOMPRESS, MASK_BDECOMPRESS)
DECLARE_INSN(pack, MATCH_PACK, MASK_PACK)
DECLARE_INSN(packu, MATCH_PACKU, MASK_PACKU)
DECLARE_INSN(packh, MATCH_PACKH, MASK_PACKH)
DECLARE_INSN(bfp, MATCH_BFP, MASK_BFP)
DECLARE_INSN(shfli, MATCH_SHFLI, MASK_SHFLI)
DECLARE_INSN(unshfli, MATCH_UNSHFLI, MASK_UNSHFLI)
DECLARE_INSN(bmatflip, MATCH_BMATFLIP, MASK_BMATFLIP)
DECLARE_INSN(crc32_d, MATCH_CRC32_D, MASK_CRC32_D)
DECLARE_INSN(crc32c_d, MATCH_CRC32C_D, MASK_CRC32C_D)
DECLARE_INSN(bmator, MATCH_BMATOR, MASK_BMATOR)
DECLARE_INSN(bmatxor, MATCH_BMATXOR, MASK_BMATXOR)
DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW)
DECLARE_INSN(slow, MATCH_SLOW, MASK_SLOW)
DECLARE_INSN(srow, MATCH_SROW, MASK_SROW)
DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW)
DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW)
DECLARE_INSN(sbclrw, MATCH_SBCLRW, MASK_SBCLRW)
DECLARE_INSN(sbsetw, MATCH_SBSETW, MASK_SBSETW)
DECLARE_INSN(sbinvw, MATCH_SBINVW, MASK_SBINVW)
DECLARE_INSN(sbextw, MATCH_SBEXTW, MASK_SBEXTW)
DECLARE_INSN(gorcw, MATCH_GORCW, MASK_GORCW)
DECLARE_INSN(grevw, MATCH_GREVW, MASK_GREVW)
DECLARE_INSN(sloiw, MATCH_SLOIW, MASK_SLOIW)
DECLARE_INSN(sroiw, MATCH_SROIW, MASK_SROIW)
DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW)
DECLARE_INSN(sbclriw, MATCH_SBCLRIW, MASK_SBCLRIW)
DECLARE_INSN(sbsetiw, MATCH_SBSETIW, MASK_SBSETIW)
DECLARE_INSN(sbinviw, MATCH_SBINVIW, MASK_SBINVIW)
DECLARE_INSN(gorciw, MATCH_GORCIW, MASK_GORCIW)
DECLARE_INSN(greviw, MATCH_GREVIW, MASK_GREVIW)
DECLARE_INSN(fslw, MATCH_FSLW, MASK_FSLW)
DECLARE_INSN(fsrw, MATCH_FSRW, MASK_FSRW)
DECLARE_INSN(fsriw, MATCH_FSRIW, MASK_FSRIW)
DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW)
DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW)
DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW)
DECLARE_INSN(sh1add_uw, MATCH_SH1ADD_UW, MASK_SH1ADD_UW)
DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW)
DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW)
DECLARE_INSN(shflw, MATCH_SHFLW, MASK_SHFLW)
DECLARE_INSN(unshflw, MATCH_UNSHFLW, MASK_UNSHFLW)
DECLARE_INSN(bcompressw, MATCH_BCOMPRESSW, MASK_BCOMPRESSW)
DECLARE_INSN(bdecompressw, MATCH_BDECOMPRESSW, MASK_BDECOMPRESSW)
DECLARE_INSN(packw, MATCH_PACKW, MASK_PACKW)
DECLARE_INSN(packuw, MATCH_PACKUW, MASK_PACKUW)
DECLARE_INSN(bfpw, MATCH_BFPW, MASK_BFPW)
DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
DECLARE_INSN(uret, MATCH_URET, MASK_URET)
DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA)
DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
DECLARE_INSN(fadd_h, MATCH_FADD_H, MASK_FADD_H)
DECLARE_INSN(fsub_h, MATCH_FSUB_H, MASK_FSUB_H)
DECLARE_INSN(fmul_h, MATCH_FMUL_H, MASK_FMUL_H)
@ -2733,20 +2721,6 @@ DECLARE_INSN(fcvt_l_h, MATCH_FCVT_L_H, MASK_FCVT_L_H)
DECLARE_INSN(fcvt_lu_h, MATCH_FCVT_LU_H, MASK_FCVT_LU_H)
DECLARE_INSN(fcvt_h_l, MATCH_FCVT_H_L, MASK_FCVT_H_L)
DECLARE_INSN(fcvt_h_lu, MATCH_FCVT_H_LU, MASK_FCVT_H_LU)
DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
DECLARE_INSN(uret, MATCH_URET, MASK_URET)
DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA)
DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
@ -2792,10 +2766,6 @@ DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
DECLARE_INSN(c_lq, MATCH_C_LQ, MASK_C_LQ)
DECLARE_INSN(c_sq, MATCH_C_SQ, MASK_C_SQ)
DECLARE_INSN(c_lqsp, MATCH_C_LQSP, MASK_C_LQSP)
DECLARE_INSN(c_sqsp, MATCH_C_SQSP, MASK_C_SQSP)
DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
@ -3410,6 +3380,10 @@ DECLARE_CSR(tselect, CSR_TSELECT)
DECLARE_CSR(tdata1, CSR_TDATA1)
DECLARE_CSR(tdata2, CSR_TDATA2)
DECLARE_CSR(tdata3, CSR_TDATA3)
DECLARE_CSR(tinfo, CSR_TINFO)
DECLARE_CSR(tcontrol, CSR_TCONTROL)
DECLARE_CSR(mcontext, CSR_MCONTEXT)
DECLARE_CSR(scontext, CSR_SCONTEXT)
DECLARE_CSR(dcsr, CSR_DCSR)
DECLARE_CSR(dpc, CSR_DPC)
DECLARE_CSR(dscratch0, CSR_DSCRATCH0)

0
riscv/insns/addu_w.h → riscv/insns/add_uw.h
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3
riscv/insns/addiwu.h
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@ -1,3 +0,0 @@
require_rv64;
require_extension('B');
WRITE_RD(zext32(insn.i_imm() + RS1));

3
riscv/insns/addwu.h
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@ -1,3 +0,0 @@
require_rv64;
require_extension('B');
WRITE_RD(zext32(RS1 + RS2));

0
riscv/insns/sbclr.h → riscv/insns/bclr.h
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0
riscv/insns/sbclri.h → riscv/insns/bclri.h
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9
riscv/insns/bcompress.h
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@ -0,0 +1,9 @@
require_extension('B');
uint64_t c = 0, i = 0, data = zext_xlen(RS1), mask = zext_xlen(RS2);
while (mask) {
uint64_t b = mask & ~((mask | (mask-1)) + 1);
c |= (data & b) >> (ctz(b) - i);
i += popcount(b);
mask -= b;
}
WRITE_RD(sext_xlen(c));

0
riscv/insns/bextw.h → riscv/insns/bcompressw.h
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0
riscv/insns/bdep.h → riscv/insns/bdecompress.h
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0
riscv/insns/bdepw.h → riscv/insns/bdecompressw.h
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10
riscv/insns/bext.h
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@ -1,9 +1,3 @@
require_extension('B');
uint64_t c = 0, i = 0, data = zext_xlen(RS1), mask = zext_xlen(RS2);
while (mask) {
uint64_t b = mask & ~((mask | (mask-1)) + 1);
c |= (data & b) >> (ctz(b) - i);
i += popcount(b);
mask -= b;
}
WRITE_RD(sext_xlen(c));
int shamt = RS2 & (xlen-1);
WRITE_RD(sext_xlen(1 & (RS1 >> shamt)));

0
riscv/insns/sbexti.h → riscv/insns/bexti.h
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0
riscv/insns/sbinv.h → riscv/insns/binv.h
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0
riscv/insns/sbinvi.h → riscv/insns/binvi.h
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0
riscv/insns/sbset.h → riscv/insns/bset.h
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0
riscv/insns/sbseti.h → riscv/insns/bseti.h
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0
riscv/insns/pcnt.h → riscv/insns/cpop.h
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0
riscv/insns/pcntw.h → riscv/insns/cpopw.h
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3
riscv/insns/sbclriw.h
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@ -1,3 +0,0 @@
require_extension('B');
int shamt = SHAMT & 31;
WRITE_RD(sext32(RS1 & ~(1LL << shamt)));

3
riscv/insns/sbclrw.h
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@ -1,3 +0,0 @@
require_extension('B');
int shamt = RS2 & 31;
WRITE_RD(sext32(RS1 & ~(1LL << shamt)));

3
riscv/insns/sbext.h
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@ -1,3 +0,0 @@
require_extension('B');
int shamt = RS2 & (xlen-1);
WRITE_RD(sext_xlen(1 & (RS1 >> shamt)));

3
riscv/insns/sbextw.h
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@ -1,3 +0,0 @@
require_extension('B');
int shamt = RS2 & 31;
WRITE_RD(sext32(1 & (RS1 >> shamt)));

3
riscv/insns/sbinviw.h
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@ -1,3 +0,0 @@
require_extension('B');
int shamt = SHAMT & 31;
WRITE_RD(sext32(RS1 ^ (1LL << shamt)));

3
riscv/insns/sbinvw.h
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@ -1,3 +0,0 @@
require_extension('B');
int shamt = RS2 & 31;
WRITE_RD(sext32(RS1 ^ (1LL << shamt)));

3
riscv/insns/sbsetiw.h
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@ -1,3 +0,0 @@
require_extension('B');
int shamt = SHAMT & 31;
WRITE_RD(sext32(RS1 | (1LL << shamt)));

3
riscv/insns/sbsetw.h
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@ -1,3 +0,0 @@
require_extension('B');
int shamt = RS2 & 31;
WRITE_RD(sext32(RS1 | (1LL << shamt)));

0
riscv/insns/sh1addu_w.h → riscv/insns/sh1add_uw.h
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0
riscv/insns/sh2addu_w.h → riscv/insns/sh2add_uw.h
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0
riscv/insns/sh3addu_w.h → riscv/insns/sh3add_uw.h
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0
riscv/insns/slliu_w.h → riscv/insns/slli_uw.h
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3
riscv/insns/subwu.h
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@ -1,3 +0,0 @@
require_rv64;
require_extension('B');
WRITE_RD(zext32(RS1 - RS2));

51
riscv/riscv.mk.in
View File

@ -334,31 +334,26 @@ riscv_insn_ext_q = \
fsub_q \
riscv_insn_ext_b = \
addiwu \
addu_w \
addwu \
add_uw \
andn \
bdep \
bdepw \
bext \
bextw \
bdecompress \
bdecompressw \
bcompress \
bcompressw \
bfp \
bfpw \
bmatflip \
bmator \
bmatxor \
sh1add \
sh1addu_w \
sh1add_uw \
sh2add \
sh2addu_w \
sh2add_uw \
sh3add \
sh3addu_w \
sh3add_uw \
clmul \
clmulh \
clmulhw \
clmulr \
clmulrw \
clmulw \
clz \
clzw \
cmix \
@ -397,35 +392,28 @@ riscv_insn_ext_b = \
packu \
packuw \
packw \
pcnt \
pcntw \
cpop \
cpopw \
rol \
rolw \
ror \
rori \
roriw \
rorw \
sbclr \
sbclri \
sbclriw \
sbclrw \
sbext \
sbexti \
sbextw \
sbinv \
sbinvi \
sbinviw \
sbinvw \
sbset \
sbseti \
sbsetiw \
sbsetw \
bclr \
bclri \
bext \
bexti \
binv \
binvi \
bset \
bseti \
sext_b \
sext_h \
shfl \
shfli \
shflw \
slliu_w \
slli_uw \
slo \
sloi \
sloiw \
@ -434,7 +422,6 @@ riscv_insn_ext_b = \
sroi \
sroiw \
srow \
subwu \
unshfl \
unshfli \
unshflw \

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