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riscv-isa-sim
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rvv: update version information 

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
pull/355/head
Chih-Min Chao 7 years ago
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      README.md

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@ -18,7 +18,7 @@ Spike supports the following RISC-V ISA features:
- D extension, v2.2
- Q extension, v2.2
- C extension, v2.0
- V extension, v0.7.1 (_requires a 64-bit host_)
- V extension, v0.8-draft-20191004, w/ Zvlsseg, w/o Zvamo/Zvediv, (_requires a 64-bit host_)
- Conformance to both RVWMO and RVTSO (Spike is sequentially consistent)
- Machine, Supervisor, and User modes, v1.11
- Debug v0.14

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