Use WRITE_RD/WRITE_FRD macros to write registers

riscv/decode.h

@@ -69,22 +69,6 @@ private:
   reg_t imm_sign() { return int64_t(int32_t(b) >> 31); }
 };
 
-template <class T>
-class write_port_t
-{
-public:
-  write_port_t(T& _t) : t(_t) {}
-  T& operator = (const T& rhs)
-  {
-    return t = rhs;
-  }
-  operator T()
-  {
-    return t;
-  }
-private:
-  T& t;
-};
 template <class T, size_t N, bool zero_reg>
 class regfile_t
 {
@@ -93,11 +77,9 @@ public:
   {
     memset(data, 0, sizeof(data));
   }
-  write_port_t<T> write_port(size_t i)
+  void write(size_t i, T value)
   {
-    if (zero_reg)
-      const_cast<T&>(data[0]) = 0;
-    return write_port_t<T>(data[i]);
+    data[i] = value;
   }
   const T& operator [] (size_t i) const
   {
@@ -113,11 +95,11 @@ private:
 #define MMU (*p->get_mmu())
 #define RS1 p->get_state()->XPR[insn.rs1()]
 #define RS2 p->get_state()->XPR[insn.rs2()]
-#define RD p->get_state()->XPR.write_port(insn.rd())
+#define WRITE_RD(value) p->get_state()->XPR.write(insn.rd(), value)
 #define FRS1 p->get_state()->FPR[insn.rs1()]
 #define FRS2 p->get_state()->FPR[insn.rs2()]
 #define FRS3 p->get_state()->FPR[insn.rs3()]
-#define FRD p->get_state()->FPR.write_port(insn.rd())
+#define WRITE_FRD(value) p->get_state()->FPR.write(insn.rd(), value)
 #define SHAMT (insn.i_imm() & 0x3F)
 #define BRANCH_TARGET (pc + insn.sb_imm())
 #define JUMP_TARGET (pc + insn.uj_imm())

riscv/insns/add.h

@@ -1 +1 @@
-RD = sext_xprlen(RS1 + RS2);
+WRITE_RD(sext_xprlen(RS1 + RS2));

riscv/insns/addi.h

@@ -1 +1 @@
-RD = sext_xprlen(RS1 + insn.i_imm());
+WRITE_RD(sext_xprlen(RS1 + insn.i_imm()));

riscv/insns/addiw.h

@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(insn.i_imm() + RS1);
+WRITE_RD(sext32(insn.i_imm() + RS1));

riscv/insns/addw.h

@@ -1,2 +1,2 @@
 require_xpr64;
-RD = sext32(RS1 + RS2);
+WRITE_RD(sext32(RS1 + RS2));

riscv/insns/amoadd_d.h

@@ -1,4 +1,4 @@
 require_xpr64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2 + v);
-RD = v;
+WRITE_RD(v);

riscv/insns/amoadd_w.h

@@ -1,3 +1,3 @@
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2 + v);
-RD = v;
+WRITE_RD(v);

riscv/insns/amoand_d.h

@@ -1,4 +1,4 @@
 require_xpr64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2 & v);
-RD = v;
+WRITE_RD(v);

riscv/insns/amoand_w.h

@@ -1,3 +1,3 @@
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2 & v);
-RD = v;
+WRITE_RD(v);

riscv/insns/amomax_d.h

@@ -1,4 +1,4 @@
 require_xpr64;
 sreg_t v = MMU.load_int64(RS1);
 MMU.store_uint64(RS1, std::max(sreg_t(RS2),v));
-RD = v;
+WRITE_RD(v);

riscv/insns/amomax_w.h

@@ -1,3 +1,3 @@
 int32_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, std::max(int32_t(RS2),v));
-RD = v;
+WRITE_RD(v);

riscv/insns/amomaxu_d.h

@@ -1,4 +1,4 @@
 require_xpr64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, std::max(RS2,v));
-RD = v;
+WRITE_RD(v);

riscv/insns/amomaxu_w.h

@@ -1,3 +1,3 @@
 uint32_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, std::max(uint32_t(RS2),v));
-RD = (int32_t)v;
+WRITE_RD((int32_t)v);

riscv/insns/amomin_d.h

@@ -1,4 +1,4 @@
 require_xpr64;
 sreg_t v = MMU.load_int64(RS1);
 MMU.store_uint64(RS1, std::min(sreg_t(RS2),v));
-RD = v;
+WRITE_RD(v);

riscv/insns/amomin_w.h

@@ -1,3 +1,3 @@
 int32_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, std::min(int32_t(RS2),v));
-RD = v;
+WRITE_RD(v);

riscv/insns/amominu_d.h

@@ -1,4 +1,4 @@
 require_xpr64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, std::min(RS2,v));
-RD = v;
+WRITE_RD(v);

riscv/insns/amominu_w.h

@@ -1,3 +1,3 @@
 uint32_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, std::min(uint32_t(RS2),v));
-RD = (int32_t)v;
+WRITE_RD((int32_t)v);

riscv/insns/amoor_d.h

@@ -1,4 +1,4 @@
 require_xpr64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2 | v);
-RD = v;
+WRITE_RD(v);

riscv/insns/amoor_w.h

@@ -1,3 +1,3 @@
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2 | v);
-RD = v;
+WRITE_RD(v);

riscv/insns/amoswap_d.h

@@ -1,4 +1,4 @@
 require_xpr64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2);
-RD = v;
+WRITE_RD(v);

riscv/insns/amoswap_w.h

@@ -1,3 +1,3 @@
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2);
-RD = v;
+WRITE_RD(v);

riscv/insns/amoxor_d.h

@@ -1,4 +1,4 @@
 require_xpr64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2 ^ v);
-RD = v;
+WRITE_RD(v);

riscv/insns/amoxor_w.h

@@ -1,3 +1,3 @@
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2 ^ v);
-RD = v;
+WRITE_RD(v);

riscv/insns/and.h

@@ -1 +1 @@
-RD = RS1 & RS2;
+WRITE_RD(RS1 & RS2);

riscv/insns/andi.h

@@ -1 +1 @@
-RD = insn.i_imm() & RS1;
+WRITE_RD(insn.i_imm() & RS1);

riscv/insns/auipc.h

@@ -1 +1 @@
-RD = sext_xprlen(insn.u_imm() + (pc >> 12 << 12));
+WRITE_RD(sext_xprlen(insn.u_imm() + (pc >> 12 << 12)));

riscv/insns/clearpcr.h

@@ -1,2 +1,2 @@
 require_supervisor;
-RD = p->set_pcr(insn.rs1(), p->get_pcr(insn.rs1()) & ~insn.i_imm());
+WRITE_RD(p->set_pcr(insn.rs1(), p->get_pcr(insn.rs1()) & ~insn.i_imm()));

riscv/insns/div.h

@@ -1,8 +1,8 @@
 sreg_t lhs = sext_xprlen(RS1);
 sreg_t rhs = sext_xprlen(RS2);
 if(rhs == 0)
-  RD = UINT64_MAX;
+  WRITE_RD(UINT64_MAX);
 else if(lhs == INT64_MIN && rhs == -1)
-  RD = lhs;
+  WRITE_RD(lhs);
 else
-  RD = sext_xprlen(lhs / rhs);
+  WRITE_RD(sext_xprlen(lhs / rhs));

riscv/insns/divu.h

@@ -1,6 +1,6 @@
 reg_t lhs = zext_xprlen(RS1);
 reg_t rhs = zext_xprlen(RS2);
 if(rhs == 0)
-  RD = UINT64_MAX;
+  WRITE_RD(UINT64_MAX);
 else
-  RD = sext_xprlen(lhs / rhs);
+  WRITE_RD(sext_xprlen(lhs / rhs));

riscv/insns/divuw.h

@@ -2,6 +2,6 @@ require_xpr64;
 reg_t lhs = zext32(RS1);
 reg_t rhs = zext32(RS2);
 if(rhs == 0)
-  RD = UINT64_MAX;
+  WRITE_RD(UINT64_MAX);
 else
-  RD = sext32(lhs / rhs);
+  WRITE_RD(sext32(lhs / rhs));

riscv/insns/divw.h

@@ -2,6 +2,6 @@ require_xpr64;
 sreg_t lhs = sext32(RS1);
 sreg_t rhs = sext32(RS2);
 if(rhs == 0)
-  RD = UINT64_MAX;
+  WRITE_RD(UINT64_MAX);
 else
-  RD = sext32(lhs / rhs);
+  WRITE_RD(sext32(lhs / rhs));

riscv/insns/fadd_d.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2);
+WRITE_FRD(f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2));
 set_fp_exceptions;

riscv/insns/fadd_s.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, 0x3f800000, FRS2);
+WRITE_FRD(f32_mulAdd(FRS1, 0x3f800000, FRS2));
 set_fp_exceptions;

riscv/insns/fcvt_d_l.h

@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-FRD = i64_to_f64(RS1);
+WRITE_FRD(i64_to_f64(RS1));
 set_fp_exceptions;

riscv/insns/fcvt_d_lu.h

@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-FRD = ui64_to_f64(RS1);
+WRITE_FRD(ui64_to_f64(RS1));
 set_fp_exceptions;

riscv/insns/fcvt_d_s.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_to_f64(FRS1);
+WRITE_FRD(f32_to_f64(FRS1));
 set_fp_exceptions;

riscv/insns/fcvt_d_w.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = i32_to_f64((int32_t)RS1);
+WRITE_FRD(i32_to_f64((int32_t)RS1));
 set_fp_exceptions;

riscv/insns/fcvt_d_wu.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = ui32_to_f64((uint32_t)RS1);
+WRITE_FRD(ui32_to_f64((uint32_t)RS1));
 set_fp_exceptions;

riscv/insns/fcvt_l_d.h

@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-RD = f64_to_i64(FRS1, RM, true);
+WRITE_RD(f64_to_i64(FRS1, RM, true));
 set_fp_exceptions;

riscv/insns/fcvt_l_s.h

@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-RD = f32_to_i64(FRS1, RM, true);
+WRITE_RD(f32_to_i64(FRS1, RM, true));
 set_fp_exceptions;

riscv/insns/fcvt_lu_d.h

@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-RD = f64_to_ui64(FRS1, RM, true);
+WRITE_RD(f64_to_ui64(FRS1, RM, true));
 set_fp_exceptions;

riscv/insns/fcvt_lu_s.h

@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-RD = f32_to_ui64(FRS1, RM, true);
+WRITE_RD(f32_to_ui64(FRS1, RM, true));
 set_fp_exceptions;

riscv/insns/fcvt_s_d.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_to_f32(FRS1);
+WRITE_FRD(f64_to_f32(FRS1));
 set_fp_exceptions;

riscv/insns/fcvt_s_l.h

@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-FRD = i64_to_f32(RS1);
+WRITE_FRD(i64_to_f32(RS1));
 set_fp_exceptions;

riscv/insns/fcvt_s_lu.h

@@ -1,5 +1,5 @@
 require_xpr64;
 require_fp;
 softfloat_roundingMode = RM;
-FRD = ui64_to_f32(RS1);
+WRITE_FRD(ui64_to_f32(RS1));
 set_fp_exceptions;

riscv/insns/fcvt_s_w.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = i32_to_f32((int32_t)RS1);
+WRITE_FRD(i32_to_f32((int32_t)RS1));
 set_fp_exceptions;

riscv/insns/fcvt_s_wu.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = ui32_to_f32((uint32_t)RS1);
+WRITE_FRD(ui32_to_f32((uint32_t)RS1));
 set_fp_exceptions;

riscv/insns/fcvt_w_d.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-RD = sext32(f64_to_i32(FRS1, RM, true));
+WRITE_RD(sext32(f64_to_i32(FRS1, RM, true)));
 set_fp_exceptions;

riscv/insns/fcvt_w_s.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-RD = sext32(f32_to_i32(FRS1, RM, true));
+WRITE_RD(sext32(f32_to_i32(FRS1, RM, true)));
 set_fp_exceptions;

riscv/insns/fcvt_wu_d.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-RD = sext32(f64_to_ui32(FRS1, RM, true));
+WRITE_RD(sext32(f64_to_ui32(FRS1, RM, true)));
 set_fp_exceptions;

riscv/insns/fcvt_wu_s.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-RD = sext32(f32_to_ui32(FRS1, RM, true));
+WRITE_RD(sext32(f32_to_ui32(FRS1, RM, true)));
 set_fp_exceptions;

riscv/insns/fdiv_d.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_div(FRS1, FRS2);
+WRITE_FRD(f64_div(FRS1, FRS2));
 set_fp_exceptions;

riscv/insns/fdiv_s.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_div(FRS1, FRS2);
+WRITE_FRD(f32_div(FRS1, FRS2));
 set_fp_exceptions;

riscv/insns/feq_d.h

@@ -1,3 +1,3 @@
 require_fp;
-RD = f64_eq(FRS1, FRS2);
+WRITE_RD(f64_eq(FRS1, FRS2));
 set_fp_exceptions;

riscv/insns/feq_s.h

@@ -1,3 +1,3 @@
 require_fp;
-RD = f32_eq(FRS1, FRS2);
+WRITE_RD(f32_eq(FRS1, FRS2));
 set_fp_exceptions;

riscv/insns/fld.h

@@ -1,2 +1,2 @@
 require_fp;
-FRD = MMU.load_int64(RS1 + insn.i_imm());
+WRITE_FRD(MMU.load_int64(RS1 + insn.i_imm()));

riscv/insns/fle_d.h

@@ -1,3 +1,3 @@
 require_fp;
-RD = f64_le(FRS1, FRS2);
+WRITE_RD(f64_le(FRS1, FRS2));
 set_fp_exceptions;

riscv/insns/fle_s.h

@@ -1,3 +1,3 @@
 require_fp;
-RD = f32_le(FRS1, FRS2);
+WRITE_RD(f32_le(FRS1, FRS2));
 set_fp_exceptions;

riscv/insns/flt_d.h

@@ -1,3 +1,3 @@
 require_fp;
-RD = f64_lt(FRS1, FRS2);
+WRITE_RD(f64_lt(FRS1, FRS2));
 set_fp_exceptions;

riscv/insns/flt_s.h

@@ -1,3 +1,3 @@
 require_fp;
-RD = f32_lt(FRS1, FRS2);
+WRITE_RD(f32_lt(FRS1, FRS2));
 set_fp_exceptions;

riscv/insns/flw.h

@@ -1,2 +1,2 @@
 require_fp;
-FRD = MMU.load_int32(RS1 + insn.i_imm());
+WRITE_FRD(MMU.load_int32(RS1 + insn.i_imm()));

riscv/insns/fmadd_d.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, FRS2, FRS3);
+WRITE_FRD(f64_mulAdd(FRS1, FRS2, FRS3));
 set_fp_exceptions;

riscv/insns/fmadd_s.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, FRS2, FRS3);
+WRITE_FRD(f32_mulAdd(FRS1, FRS2, FRS3));
 set_fp_exceptions;

riscv/insns/fmax_d.h

@@ -1,4 +1,4 @@
 require_fp;
-FRD = isNaNF64UI(FRS2) || f64_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */
-      ? FRS1 : FRS2;
+WRITE_FRD(isNaNF64UI(FRS2) || f64_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */
+      ? FRS1 : FRS2);
 set_fp_exceptions;

riscv/insns/fmax_s.h

@@ -1,4 +1,4 @@
 require_fp;
-FRD = isNaNF32UI(FRS2) || f32_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */
-      ? FRS1 : FRS2;
+WRITE_FRD(isNaNF32UI(FRS2) || f32_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */
+      ? FRS1 : FRS2);
 set_fp_exceptions;

riscv/insns/fmin_d.h

@@ -1,4 +1,4 @@
 require_fp;
-FRD = isNaNF64UI(FRS2) || f64_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */
-      ? FRS1 : FRS2;
+WRITE_FRD(isNaNF64UI(FRS2) || f64_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */
+      ? FRS1 : FRS2);
 set_fp_exceptions;

riscv/insns/fmin_s.h

@@ -1,4 +1,4 @@
 require_fp;
-FRD = isNaNF32UI(FRS2) || f32_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */
-      ? FRS1 : FRS2;
+WRITE_FRD(isNaNF32UI(FRS2) || f32_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */
+      ? FRS1 : FRS2);
 set_fp_exceptions;

riscv/insns/fmsub_d.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN);
+WRITE_FRD(f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN));
 set_fp_exceptions;

riscv/insns/fmsub_s.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN);
+WRITE_FRD(f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN));
 set_fp_exceptions;

riscv/insns/fmul_d.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint64_t)INT64_MIN);
+WRITE_FRD(f64_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint64_t)INT64_MIN));
 set_fp_exceptions;

riscv/insns/fmul_s.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint32_t)INT32_MIN);
+WRITE_FRD(f32_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint32_t)INT32_MIN));
 set_fp_exceptions;

riscv/insns/fmv_d_x.h

@@ -1,3 +1,3 @@
 require_xpr64;
 require_fp;
-FRD = RS1;
+WRITE_FRD(RS1);

riscv/insns/fmv_s_x.h

@@ -1,2 +1,2 @@
 require_fp;
-FRD = RS1;
+WRITE_FRD(RS1);

riscv/insns/fmv_x_d.h

@@ -1,3 +1,3 @@
 require_xpr64;
 require_fp;
-RD = FRS1;
+WRITE_RD(FRS1);

riscv/insns/fmv_x_s.h

@@ -1,2 +1,2 @@
 require_fp;
-RD = sext32(FRS1);
+WRITE_RD(sext32(FRS1));

riscv/insns/fnmadd_d.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3 ^ (uint64_t)INT64_MIN);
+WRITE_FRD(f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3 ^ (uint64_t)INT64_MIN));
 set_fp_exceptions;

riscv/insns/fnmadd_s.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3 ^ (uint32_t)INT32_MIN);
+WRITE_FRD(f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3 ^ (uint32_t)INT32_MIN));
 set_fp_exceptions;

riscv/insns/fnmsub_d.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3);
+WRITE_FRD(f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3));
 set_fp_exceptions;

riscv/insns/fnmsub_s.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3);
+WRITE_FRD(f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3));
 set_fp_exceptions;

riscv/insns/frsr.h

@@ -1,2 +1,2 @@
 require_fp;
-RD = p->get_fsr();
+WRITE_RD(p->get_fsr());

riscv/insns/fsgnj_d.h

@@ -1,2 +1,2 @@
 require_fp;
-FRD = (FRS1 &~ INT64_MIN) | (FRS2 & INT64_MIN);
+WRITE_FRD((FRS1 &~ INT64_MIN) | (FRS2 & INT64_MIN));

riscv/insns/fsgnj_s.h

@@ -1,2 +1,2 @@
 require_fp;
-FRD = (FRS1 &~ (uint32_t)INT32_MIN) | (FRS2 & (uint32_t)INT32_MIN);
+WRITE_FRD((FRS1 &~ (uint32_t)INT32_MIN) | (FRS2 & (uint32_t)INT32_MIN));

riscv/insns/fsgnjn_d.h

@@ -1,2 +1,2 @@
 require_fp;
-FRD = (FRS1 &~ INT64_MIN) | ((~FRS2) & INT64_MIN);
+WRITE_FRD((FRS1 &~ INT64_MIN) | ((~FRS2) & INT64_MIN));

riscv/insns/fsgnjn_s.h

@@ -1,2 +1,2 @@
 require_fp;
-FRD = (FRS1 &~ (uint32_t)INT32_MIN) | ((~FRS2) & (uint32_t)INT32_MIN);
+WRITE_FRD((FRS1 &~ (uint32_t)INT32_MIN) | ((~FRS2) & (uint32_t)INT32_MIN));

riscv/insns/fsgnjx_d.h

@@ -1,2 +1,2 @@
 require_fp;
-FRD = FRS1 ^ (FRS2 & INT64_MIN);
+WRITE_FRD(FRS1 ^ (FRS2 & INT64_MIN));

riscv/insns/fsgnjx_s.h

@@ -1,2 +1,2 @@
 require_fp;
-FRD = FRS1 ^ (FRS2 & (uint32_t)INT32_MIN);
+WRITE_FRD(FRS1 ^ (FRS2 & (uint32_t)INT32_MIN));

riscv/insns/fsqrt_d.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_sqrt(FRS1);
+WRITE_FRD(f64_sqrt(FRS1));
 set_fp_exceptions;

riscv/insns/fsqrt_s.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_sqrt(FRS1);
+WRITE_FRD(f32_sqrt(FRS1));
 set_fp_exceptions;

riscv/insns/fssr.h

@@ -1,2 +1,2 @@
 require_fp;
-RD = p->set_fsr(RS1);
+WRITE_RD(p->set_fsr(RS1));

riscv/insns/fsub_d.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2 ^ (uint64_t)INT64_MIN);
+WRITE_FRD(f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2 ^ (uint64_t)INT64_MIN));
 set_fp_exceptions;

riscv/insns/fsub_s.h

@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, 0x3f800000, FRS2 ^ (uint32_t)INT32_MIN);
+WRITE_FRD(f32_mulAdd(FRS1, 0x3f800000, FRS2 ^ (uint32_t)INT32_MIN));
 set_fp_exceptions;

riscv/insns/jal.h

@@ -1,2 +1,2 @@
-RD = npc;
+WRITE_RD(npc);
 set_pc(JUMP_TARGET);

riscv/insns/jalr.h

@@ -1,3 +1,3 @@
 reg_t temp = RS1;
-RD = npc;
+WRITE_RD(npc);
 set_pc((temp + insn.i_imm()) & ~1);

riscv/insns/lb.h

@@ -1 +1 @@
-RD = MMU.load_int8(RS1 + insn.i_imm());
+WRITE_RD(MMU.load_int8(RS1 + insn.i_imm()));

riscv/insns/lbu.h

@@ -1 +1 @@
-RD = MMU.load_uint8(RS1 + insn.i_imm());
+WRITE_RD(MMU.load_uint8(RS1 + insn.i_imm()));

riscv/insns/ld.h

@@ -1,2 +1,2 @@
 require_xpr64;
-RD = MMU.load_int64(RS1 + insn.i_imm());
+WRITE_RD(MMU.load_int64(RS1 + insn.i_imm()));

riscv/insns/lh.h

@@ -1 +1 @@
-RD = MMU.load_int16(RS1 + insn.i_imm());
+WRITE_RD(MMU.load_int16(RS1 + insn.i_imm()));

riscv/insns/lhu.h

@@ -1 +1 @@
-RD = MMU.load_uint16(RS1 + insn.i_imm());
+WRITE_RD(MMU.load_uint16(RS1 + insn.i_imm()));

riscv/insns/lr_d.h

@@ -1,3 +1,3 @@
 require_xpr64;
 p->get_state()->load_reservation = RS1;
-RD = MMU.load_int64(RS1);
+WRITE_RD(MMU.load_int64(RS1));

riscv/insns/lr_w.h

@@ -1,2 +1,2 @@
 p->get_state()->load_reservation = RS1;
-RD = MMU.load_int32(RS1);
+WRITE_RD(MMU.load_int32(RS1));