Support setting ISA/subsets with --isa flag

Default is RV64IMAFDC.  Can do things like

  --isa=RV32 (which implies IMAFDC)
  --isa=IM (which implies RV64)
  --isa=RV64IMAFDXhwacha

config.h.in

@@ -33,21 +33,12 @@
 /* Define if subproject MCPPBS_SPROJ_NORM is enabled */
 #undef RISCV_ENABLED
 
-/* Define if 64-bit mode is supported */
-#undef RISCV_ENABLE_64BIT
-
 /* Enable commit log generation */
 #undef RISCV_ENABLE_COMMITLOG
 
-/* Define if floating-point instructions are supported */
-#undef RISCV_ENABLE_FPU
-
 /* Enable PC histogram generation */
 #undef RISCV_ENABLE_HISTOGRAM
 
-/* Define if RISC-V Compressed is supported */
-#undef RISCV_ENABLE_RVC
-
 /* Define if subproject MCPPBS_SPROJ_NORM is enabled */
 #undef SOFTFLOAT_ENABLED
 

configure

@@ -664,9 +664,6 @@ enable_option_checking
 enable_stow
 enable_optional_subprojects
 with_fesvr
-enable_fpu
-enable_rvc
-enable_64bit
 enable_commitlog
 enable_histogram
 '
@@ -1300,9 +1297,6 @@ Optional Features:
   --enable-stow           Enable stow-based install
   --enable-optional-subprojects
                           Enable all optional subprojects
-  --disable-fpu           Disable floating-point
-  --disable-rvc           Disable RISC-V Compressed
-  --disable-64bit         Disable 64-bit mode
   --enable-commitlog      Enable commit log generation
   --enable-histogram      Enable PC histogram generation
 
@@ -3979,6 +3973,67 @@ ac_link='$CXX -o conftest$ac_exeext $CXXFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ex
 ac_compiler_gnu=$ac_cv_cxx_compiler_gnu
 
 
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for library containing dlopen" >&5
+$as_echo_n "checking for library containing dlopen... " >&6; }
+if ${ac_cv_search_dlopen+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  ac_func_search_save_LIBS=$LIBS
+cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+
+/* Override any GCC internal prototype to avoid an error.
+   Use char because int might match the return type of a GCC
+   builtin and then its argument prototype would still apply.  */
+#ifdef __cplusplus
+extern "C"
+#endif
+char dlopen ();
+int
+main ()
+{
+return dlopen ();
+  ;
+  return 0;
+}
+_ACEOF
+for ac_lib in '' dl dld; do
+  if test -z "$ac_lib"; then
+    ac_res="none required"
+  else
+    ac_res=-l$ac_lib
+    LIBS="-l$ac_lib  $ac_func_search_save_LIBS"
+  fi
+  if ac_fn_cxx_try_link "$LINENO"; then :
+  ac_cv_search_dlopen=$ac_res
+fi
+rm -f core conftest.err conftest.$ac_objext \
+    conftest$ac_exeext
+  if ${ac_cv_search_dlopen+:} false; then :
+  break
+fi
+done
+if ${ac_cv_search_dlopen+:} false; then :
+
+else
+  ac_cv_search_dlopen=no
+fi
+rm conftest.$ac_ext
+LIBS=$ac_func_search_save_LIBS
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_search_dlopen" >&5
+$as_echo "$ac_cv_search_dlopen" >&6; }
+ac_res=$ac_cv_search_dlopen
+if test "$ac_res" != no; then :
+  test "$ac_res" = "none required" || LIBS="$ac_res $LIBS"
+
+else
+
+  as_fn_error $? "unable to find the dlopen() function" "$LINENO" 5
+
+fi
+
+
 
 # Check whether --with-fesvr was given.
 if test "${with_fesvr+set}" = set; then :
@@ -4086,45 +4141,6 @@ else
 fi
 
 
-# Check whether --enable-fpu was given.
-if test "${enable_fpu+set}" = set; then :
-  enableval=$enable_fpu;
-fi
-
-if test "x$enable_fpu" != "xno"; then :
-
-
-$as_echo "#define RISCV_ENABLE_FPU /**/" >>confdefs.h
-
-
-fi
-
-# Check whether --enable-rvc was given.
-if test "${enable_rvc+set}" = set; then :
-  enableval=$enable_rvc;
-fi
-
-if test "x$enable_rvc" != "xno"; then :
-
-
-$as_echo "#define RISCV_ENABLE_RVC /**/" >>confdefs.h
-
-
-fi
-
-# Check whether --enable-64bit was given.
-if test "${enable_64bit+set}" = set; then :
-  enableval=$enable_64bit;
-fi
-
-if test "x$enable_64bit" != "xno"; then :
-
-
-$as_echo "#define RISCV_ENABLE_64BIT /**/" >>confdefs.h
-
-
-fi
-
 # Check whether --enable-commitlog was given.
 if test "${enable_commitlog+set}" = set; then :
   enableval=$enable_commitlog;
@@ -4330,66 +4346,6 @@ $as_echo "$as_me: configuring default subproject : spike_main" >&6;}
 
 $as_echo "#define SPIKE_MAIN_ENABLED /**/" >>confdefs.h
 
-      { $as_echo "$as_me:${as_lineno-$LINENO}: checking for library containing dlopen" >&5
-$as_echo_n "checking for library containing dlopen... " >&6; }
-if ${ac_cv_search_dlopen+:} false; then :
-  $as_echo_n "(cached) " >&6
-else
-  ac_func_search_save_LIBS=$LIBS
-cat confdefs.h - <<_ACEOF >conftest.$ac_ext
-/* end confdefs.h.  */
-
-/* Override any GCC internal prototype to avoid an error.
-   Use char because int might match the return type of a GCC
-   builtin and then its argument prototype would still apply.  */
-#ifdef __cplusplus
-extern "C"
-#endif
-char dlopen ();
-int
-main ()
-{
-return dlopen ();
-  ;
-  return 0;
-}
-_ACEOF
-for ac_lib in '' dl dld; do
-  if test -z "$ac_lib"; then
-    ac_res="none required"
-  else
-    ac_res=-l$ac_lib
-    LIBS="-l$ac_lib  $ac_func_search_save_LIBS"
-  fi
-  if ac_fn_cxx_try_link "$LINENO"; then :
-  ac_cv_search_dlopen=$ac_res
-fi
-rm -f core conftest.err conftest.$ac_objext \
-    conftest$ac_exeext
-  if ${ac_cv_search_dlopen+:} false; then :
-  break
-fi
-done
-if ${ac_cv_search_dlopen+:} false; then :
-
-else
-  ac_cv_search_dlopen=no
-fi
-rm conftest.$ac_ext
-LIBS=$ac_func_search_save_LIBS
-fi
-{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_search_dlopen" >&5
-$as_echo "$ac_cv_search_dlopen" >&6; }
-ac_res=$ac_cv_search_dlopen
-if test "$ac_res" != no; then :
-  test "$ac_res" = "none required" || LIBS="$ac_res $LIBS"
-
-else
-
-  as_fn_error $? "unable to find the dlopen() function" "$LINENO" 5
-
-fi
-
 
 
 

riscv/decode.h

@@ -45,14 +45,6 @@ const int NFPR = 32;
 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
 
-#ifdef RISCV_ENABLE_RVC
-# define INSN_ALIGNMENT 2
-# define require_rvc
-#else
-# define INSN_ALIGNMENT 4
-# define require_rvc throw trap_illegal_instruction()
-#endif
-
 #define insn_length(x) \
   (((x) & 0x03) < 0x03 ? 2 : \
    ((x) & 0x1f) < 0x1f ? 4 : \
@@ -173,11 +165,8 @@ private:
 #define require_privilege(p) if (get_field(STATE.mstatus, MSTATUS_PRV) < (p)) throw trap_illegal_instruction()
 #define require_rv64 if(unlikely(xlen != 64)) throw trap_illegal_instruction()
 #define require_rv32 if(unlikely(xlen != 32)) throw trap_illegal_instruction()
-#ifdef RISCV_ENABLE_FPU
-# define require_fp if (unlikely((STATE.mstatus & MSTATUS_FS) == 0)) throw trap_illegal_instruction()
-#else
-# define require_fp throw trap_illegal_instruction()
-#endif
+#define require_extension(s) if (!p->supports_extension(s)) throw trap_illegal_instruction()
+#define require_fp if (unlikely((STATE.mstatus & MSTATUS_FS) == 0)) throw trap_illegal_instruction()
 #define require_accelerator if (unlikely((STATE.mstatus & MSTATUS_XS) == 0)) throw trap_illegal_instruction()
 
 #define set_fp_exceptions ({ STATE.fflags |= softfloat_exceptionFlags; \
@@ -189,7 +178,7 @@ private:
 #define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen))
 
 #define set_pc(x) \
-  do { if ((x) & (INSN_ALIGNMENT-1)) \
+  do { if (unlikely(((x) & 2)) && !p->supports_extension('C')) \
          throw trap_instruction_address_misaligned(x); \
        npc = sext_xlen(x); \
      } while(0)

riscv/encoding.h

@@ -48,7 +48,8 @@
 #define VM_MBB   1
 #define VM_MBBID 2
 #define VM_SV32  4
-#define VM_SV43  5
+#define VM_SV39  5
+#define VM_SV48  6
 
 #define UA_RV32  0
 #define UA_RV64  4
@@ -69,7 +70,8 @@
 #define PTE_R      0x040 // Referenced
 #define PTE_D      0x080 // Dirty
 #define PTE_SOFT   0x300 // Reserved for Software
-#define PTE_PPN_SHIFT 10
+#define RV64_PTE_PPN_SHIFT 26
+#define RV32_PTE_PPN_SHIFT 10
 #define PTE_TYPE_INVALID 0
 #define PTE_TYPE_TABLE   1
 #define PTE_TYPE_U       2
@@ -105,13 +107,13 @@
 # define MSTATUS_HA MSTATUS64_HA
 # define MSTATUS_SD MSTATUS64_SD
 # define SSTATUS_SD SSTATUS64_SD
-# define RISCV_PGLEVELS 3 /* Sv39 */
 # define RISCV_PGLEVEL_BITS 9
+# define PTE_PPN_SHIFT RV64_PTE_PPN_SHIFT
 #else
 # define MSTATUS_SD MSTATUS32_SD
 # define SSTATUS_SD SSTATUS32_SD
-# define RISCV_PGLEVELS 2 /* Sv32 */
 # define RISCV_PGLEVEL_BITS 10
+# define PTE_PPN_SHIFT RV32_PTE_PPN_SHIFT
 #endif
 #define RISCV_PGSHIFT 12
 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT)

riscv/insns/amoadd_d.h

@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2 + v);

riscv/insns/amoadd_w.h

@@ -1,3 +1,4 @@
+require_extension('A');
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2 + v);
 WRITE_RD(v);

riscv/insns/amoand_d.h

@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2 & v);

riscv/insns/amoand_w.h

@@ -1,3 +1,4 @@
+require_extension('A');
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2 & v);
 WRITE_RD(v);

riscv/insns/amomax_d.h

@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 sreg_t v = MMU.load_int64(RS1);
 MMU.store_uint64(RS1, std::max(sreg_t(RS2),v));

riscv/insns/amomax_w.h

@@ -1,3 +1,4 @@
+require_extension('A');
 int32_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, std::max(int32_t(RS2),v));
 WRITE_RD(v);

riscv/insns/amomaxu_d.h

@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, std::max(RS2,v));

riscv/insns/amomaxu_w.h

@@ -1,3 +1,4 @@
+require_extension('A');
 uint32_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, std::max(uint32_t(RS2),v));
 WRITE_RD((int32_t)v);

riscv/insns/amomin_d.h

@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 sreg_t v = MMU.load_int64(RS1);
 MMU.store_uint64(RS1, std::min(sreg_t(RS2),v));

riscv/insns/amomin_w.h

@@ -1,3 +1,4 @@
+require_extension('A');
 int32_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, std::min(int32_t(RS2),v));
 WRITE_RD(v);

riscv/insns/amominu_d.h

@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, std::min(RS2,v));

riscv/insns/amominu_w.h

@@ -1,3 +1,4 @@
+require_extension('A');
 uint32_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, std::min(uint32_t(RS2),v));
 WRITE_RD((int32_t)v);

riscv/insns/amoor_d.h

@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2 | v);

riscv/insns/amoor_w.h

@@ -1,3 +1,4 @@
+require_extension('A');
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2 | v);
 WRITE_RD(v);

riscv/insns/amoswap_d.h

@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2);

riscv/insns/amoswap_w.h

@@ -1,3 +1,4 @@
+require_extension('A');
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2);
 WRITE_RD(v);

riscv/insns/amoxor_d.h

@@ -1,3 +1,4 @@
+require_extension('A');
 require_rv64;
 reg_t v = MMU.load_uint64(RS1);
 MMU.store_uint64(RS1, RS2 ^ v);

riscv/insns/amoxor_w.h

@@ -1,3 +1,4 @@
+require_extension('A');
 reg_t v = MMU.load_int32(RS1);
 MMU.store_uint32(RS1, RS2 ^ v);
 WRITE_RD(v);

riscv/insns/c_add.h

@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 WRITE_RD(sext_xlen(RVC_RS1 + RVC_RS2));

riscv/insns/c_addi.h

@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 WRITE_RD(sext_xlen(RVC_RS2 + insn.rvc_imm()));

riscv/insns/c_addi4.h

@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 WRITE_RD(sext_xlen(RVC_RS2 + insn.rvc_lwsp_imm()));

riscv/insns/c_addiw.h

@@ -1,3 +1,3 @@
-require_rvc;
+require_extension('C');
 require_rv64;
 WRITE_RD(sext32(RVC_RS2 + insn.rvc_imm()));

riscv/insns/c_addw.h

@@ -1,3 +1,3 @@
-require_rvc;
+require_extension('C');
 require_rv64;
 WRITE_RD(sext32(RVC_RS1 + RVC_RS2));

riscv/insns/c_beqz.h

@@ -1,3 +1,3 @@
-require_rvc;
+require_extension('C');
 if (RVC_RS1S == 0)
   set_pc(pc + insn.rvc_b_imm());

riscv/insns/c_bnez.h

@@ -1,3 +1,3 @@
-require_rvc;
+require_extension('C');
 if (RVC_RS1S != 0)
   set_pc(pc + insn.rvc_b_imm());

riscv/insns/c_j.h

@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 set_pc(pc + insn.rvc_j_imm());

riscv/insns/c_jalr.h

@@ -1,4 +1,4 @@
-require_rvc;
+require_extension('C');
 reg_t tmp = npc;
 set_pc(RVC_RS1 & ~reg_t(1));
 WRITE_RD(tmp);

riscv/insns/c_ld.h

@@ -1,3 +1,3 @@
-require_rvc;
+require_extension('C');
 require_rv64;
 WRITE_RVC_RDS(MMU.load_int64(RVC_RS1S + insn.rvc_ld_imm()));

riscv/insns/c_ldsp.h

@@ -1,3 +1,3 @@
-require_rvc;
+require_extension('C');
 require_rv64;
 WRITE_RD(MMU.load_int64(RVC_SP + insn.rvc_ldsp_imm()));

riscv/insns/c_li.h

@@ -1,4 +1,4 @@
-require_rvc;
+require_extension('C');
 if (insn.rvc_rd() == 0) {
   if (insn.rvc_imm() == -32) // c.sbreak
     throw trap_breakpoint();

riscv/insns/c_lui.h

@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 WRITE_RD(insn.rvc_imm() << 12);

riscv/insns/c_lw.h

@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 WRITE_RVC_RDS(MMU.load_int32(RVC_RS1S + insn.rvc_lw_imm()));

riscv/insns/c_lwsp.h

@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 WRITE_RD(MMU.load_int32(RVC_SP + insn.rvc_lwsp_imm()));

riscv/insns/c_mv.h

@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 WRITE_RD(RVC_RS1);

riscv/insns/c_sd.h

@@ -1,3 +1,3 @@
-require_rvc;
+require_extension('C');
 require_rv64;
 MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S);

riscv/insns/c_sdsp.h

@@ -1,3 +1,3 @@
-require_rvc;
+require_extension('C');
 require_rv64;
 MMU.store_uint64(RVC_SP + insn.rvc_ldsp_imm(), RVC_RS2);

riscv/insns/c_slli.h

@@ -1,4 +1,4 @@
-require_rvc;
+require_extension('C');
 if (insn.rvc_imm() >= xlen)
   throw trap_illegal_instruction();
 WRITE_RD(sext_xlen(RVC_RS2 << insn.rvc_imm()));

riscv/insns/c_sw.h

@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_RS2S);

riscv/insns/c_swsp.h

@@ -1,2 +1,2 @@
-require_rvc;
+require_extension('C');
 MMU.store_uint32(RVC_SP + insn.rvc_lwsp_imm(), RVC_RS2);

riscv/insns/div.h

@@ -1,3 +1,4 @@
+require_extension('M');
 sreg_t lhs = sext_xlen(RS1);
 sreg_t rhs = sext_xlen(RS2);
 if(rhs == 0)

riscv/insns/divu.h

@@ -1,3 +1,4 @@
+require_extension('M');
 reg_t lhs = zext_xlen(RS1);
 reg_t rhs = zext_xlen(RS2);
 if(rhs == 0)

riscv/insns/divuw.h

@@ -1,3 +1,4 @@
+require_extension('M');
 require_rv64;
 reg_t lhs = zext32(RS1);
 reg_t rhs = zext32(RS2);

riscv/insns/divw.h

@@ -1,3 +1,4 @@
+require_extension('M');
 require_rv64;
 sreg_t lhs = sext32(RS1);
 sreg_t rhs = sext32(RS2);

riscv/insns/fadd_d.h

@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2));

riscv/insns/fadd_s.h

@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f32_mulAdd(FRS1, 0x3f800000, FRS2));

riscv/insns/fclass_d.h

@@ -1,2 +1,3 @@
+require_extension('D');
 require_fp;
 WRITE_RD(f64_classify(FRS1));

riscv/insns/fclass_s.h

@@ -1,2 +1,3 @@
+require_extension('F');
 require_fp;
 WRITE_RD(f32_classify(FRS1));

riscv/insns/fcvt_d_l.h

@@ -1,3 +1,4 @@
+require_extension('D');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;

riscv/insns/fcvt_d_lu.h

@@ -1,3 +1,4 @@
+require_extension('D');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;

riscv/insns/fcvt_d_s.h

@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f32_to_f64(FRS1));

riscv/insns/fcvt_d_w.h

@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(i32_to_f64((int32_t)RS1));

riscv/insns/fcvt_d_wu.h

@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(ui32_to_f64((uint32_t)RS1));

riscv/insns/fcvt_l_d.h

@@ -1,3 +1,4 @@
+require_extension('D');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;

riscv/insns/fcvt_l_s.h

@@ -1,3 +1,4 @@
+require_extension('F');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;

riscv/insns/fcvt_lu_d.h

@@ -1,3 +1,4 @@
+require_extension('D');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;

riscv/insns/fcvt_lu_s.h

@@ -1,3 +1,4 @@
+require_extension('F');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;

riscv/insns/fcvt_s_d.h

@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f64_to_f32(FRS1));

riscv/insns/fcvt_s_l.h

@@ -1,3 +1,4 @@
+require_extension('F');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;

riscv/insns/fcvt_s_lu.h

@@ -1,3 +1,4 @@
+require_extension('F');
 require_rv64;
 require_fp;
 softfloat_roundingMode = RM;

riscv/insns/fcvt_s_w.h

@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(i32_to_f32((int32_t)RS1));

riscv/insns/fcvt_s_wu.h

@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(ui32_to_f32((uint32_t)RS1));

riscv/insns/fcvt_w_d.h

@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_RD(sext32(f64_to_i32(FRS1, RM, true)));

riscv/insns/fcvt_w_s.h

@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_RD(sext32(f32_to_i32(FRS1, RM, true)));

riscv/insns/fcvt_wu_d.h

@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_RD(sext32(f64_to_ui32(FRS1, RM, true)));

riscv/insns/fcvt_wu_s.h

@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_RD(sext32(f32_to_ui32(FRS1, RM, true)));

riscv/insns/fdiv_d.h

@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f64_div(FRS1, FRS2));

riscv/insns/fdiv_s.h

@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f32_div(FRS1, FRS2));

riscv/insns/feq_d.h

@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 WRITE_RD(f64_eq(FRS1, FRS2));
 set_fp_exceptions;

riscv/insns/feq_s.h

@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 WRITE_RD(f32_eq(FRS1, FRS2));
 set_fp_exceptions;

riscv/insns/fld.h

@@ -1,2 +1,3 @@
+require_extension('D');
 require_fp;
 WRITE_FRD(MMU.load_int64(RS1 + insn.i_imm()));

riscv/insns/fle_d.h

@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 WRITE_RD(f64_le(FRS1, FRS2));
 set_fp_exceptions;

riscv/insns/fle_s.h

@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 WRITE_RD(f32_le(FRS1, FRS2));
 set_fp_exceptions;

riscv/insns/flt_d.h

@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 WRITE_RD(f64_lt(FRS1, FRS2));
 set_fp_exceptions;

riscv/insns/flt_s.h

@@ -1,3 +1,4 @@
+require_extension('F');
 require_fp;
 WRITE_RD(f32_lt(FRS1, FRS2));
 set_fp_exceptions;

riscv/insns/flw.h

@@ -1,2 +1,3 @@
+require_extension('F');
 require_fp;
 WRITE_FRD(MMU.load_int32(RS1 + insn.i_imm()));

riscv/insns/fmadd_d.h

@@ -1,3 +1,4 @@
+require_extension('D');
 require_fp;
 softfloat_roundingMode = RM;
 WRITE_FRD(f64_mulAdd(FRS1, FRS2, FRS3));