From c3f60c99f26909eb92ac88d720e9a64106712275 Mon Sep 17 00:00:00 2001 From: YenHaoChen Date: Fri, 29 Mar 2024 09:10:00 +0800 Subject: [PATCH] AIA: Add read-only 0 iprio array for machine level --- riscv/csr_init.cc | 23 ++++++++++++++++++++++- riscv/processor.h | 1 + 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/riscv/csr_init.cc b/riscv/csr_init.cc index 5cbedb7f..d3d5c014 100644 --- a/riscv/csr_init.cc +++ b/riscv/csr_init.cc @@ -12,6 +12,24 @@ void state_t::add_csr(reg_t addr, const csr_t_p& csr) #define add_supervisor_csr(addr, csr) add_const_ext_csr('S', addr, csr) #define add_hypervisor_csr(addr, csr) add_ext_csr('H', addr, csr) +void state_t::add_ireg_proxy(processor_t* const proc, sscsrind_reg_csr_t::sscsrind_reg_csr_t_p ireg) +{ + // This assumes xlen is always max_xlen, which is true today (see + // mstatus_csr_t::unlogged_write()): + auto xlen = proc->get_isa().get_max_xlen(); + + const reg_t iprio0_addr = 0x30; + for (int i=0; i<16; i+=2) { + csr_t_p iprio = std::make_shared(proc, iprio0_addr + i, 0); + if (xlen == 32) { + ireg->add_ireg_proxy(iprio0_addr + i, std::make_shared(proc, iprio0_addr + i, iprio)); + ireg->add_ireg_proxy(iprio0_addr + i + 1, std::make_shared(proc, iprio0_addr + i + 1, iprio)); + } else { + ireg->add_ireg_proxy(iprio0_addr + i, iprio); + } + } +} + void state_t::csr_init(processor_t* const proc, reg_t max_isa) { // This assumes xlen is always max_xlen, which is true today (see @@ -363,7 +381,10 @@ void state_t::csr_init(processor_t* const proc, reg_t max_isa) csr_t_p miselect = std::make_shared(proc, CSR_MISELECT, 0); add_csr(CSR_MISELECT, miselect); - const reg_t mireg_csrs[] = { CSR_MIREG, CSR_MIREG2, CSR_MIREG3, CSR_MIREG4, CSR_MIREG5, CSR_MIREG6 }; + sscsrind_reg_csr_t::sscsrind_reg_csr_t_p mireg; + add_csr(CSR_MIREG, mireg = std::make_shared(proc, CSR_MIREG, miselect)); + add_ireg_proxy(proc, mireg); + const reg_t mireg_csrs[] = { CSR_MIREG2, CSR_MIREG3, CSR_MIREG4, CSR_MIREG5, CSR_MIREG6 }; for (auto csr : mireg_csrs) add_csr(csr, std::make_shared(proc, csr, miselect)); } diff --git a/riscv/processor.h b/riscv/processor.h index 5f84d748..994e92d7 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -70,6 +70,7 @@ typedef std::vector> commit_log_mem_t; // architectural state of a RISC-V hart struct state_t { + void add_ireg_proxy(processor_t* const proc, sscsrind_reg_csr_t::sscsrind_reg_csr_t_p ireg); void reset(processor_t* const proc, reg_t max_isa); void add_csr(reg_t addr, const csr_t_p& csr);