Update encoding.h to add instructions for BF16 extensions

riscv/encoding.h

@@ -4,7 +4,7 @@
 
 /*
  * This file is auto-generated by running 'make' in
- * https://github.com/riscv/riscv-opcodes (5adef50)
+ * https://github.com/riscv/riscv-opcodes (8d70e77)
  */
 
 #ifndef RISCV_CSR_ENCODING_H
@@ -751,6 +751,8 @@
 #define MASK_FCLASS_Q 0xfff0707f
 #define MATCH_FCLASS_S 0xe0001053
 #define MASK_FCLASS_S 0xfff0707f
+#define MATCH_FCVT_BF16_S 0x44800053
+#define MASK_FCVT_BF16_S 0xfff0007f
 #define MATCH_FCVT_D_H 0x42200053
 #define MASK_FCVT_D_H 0xfff0007f
 #define MATCH_FCVT_D_L 0xd2200053
@@ -809,6 +811,8 @@
 #define MASK_FCVT_Q_W 0xfff0007f
 #define MATCH_FCVT_Q_WU 0xd6100053
 #define MASK_FCVT_Q_WU 0xfff0007f
+#define MATCH_FCVT_S_BF16 0x40600053
+#define MASK_FCVT_S_BF16 0xfff0007f
 #define MATCH_FCVT_S_D 0x40100053
 #define MASK_FCVT_S_D 0xfff0007f
 #define MATCH_FCVT_S_H 0x40200053
@@ -2165,6 +2169,8 @@
 #define MASK_VFNCVT_X_F_W 0xfc0ff07f
 #define MATCH_VFNCVT_XU_F_W 0x48081057
 #define MASK_VFNCVT_XU_F_W 0xfc0ff07f
+#define MATCH_VFNCVTBF16_F_F_W 0x480e9057
+#define MASK_VFNCVTBF16_F_F_W 0xfc0ff07f
 #define MATCH_VFNMACC_VF 0xb4005057
 #define MASK_VFNMACC_VF 0xfc00707f
 #define MATCH_VFNMACC_VV 0xb4001057
@@ -2241,10 +2247,16 @@
 #define MASK_VFWCVT_X_F_V 0xfc0ff07f
 #define MATCH_VFWCVT_XU_F_V 0x48041057
 #define MASK_VFWCVT_XU_F_V 0xfc0ff07f
+#define MATCH_VFWCVTBF16_F_F_V 0x48069057
+#define MASK_VFWCVTBF16_F_F_V 0xfc0ff07f
 #define MATCH_VFWMACC_VF 0xf0005057
 #define MASK_VFWMACC_VF 0xfc00707f
 #define MATCH_VFWMACC_VV 0xf0001057
 #define MASK_VFWMACC_VV 0xfc00707f
+#define MATCH_VFWMACCBF16_VF 0xec005057
+#define MASK_VFWMACCBF16_VF 0xfc00707f
+#define MATCH_VFWMACCBF16_VV 0xec001057
+#define MASK_VFWMACCBF16_VV 0xfc00707f
 #define MATCH_VFWMSAC_VF 0xf8005057
 #define MASK_VFWMSAC_VF 0xfc00707f
 #define MATCH_VFWMSAC_VV 0xf8001057
@@ -3392,8 +3404,11 @@
 #define INSN_FIELD_AMOOP 0xf8000000
 #define INSN_FIELD_NF 0xe0000000
 #define INSN_FIELD_SIMM5 0xf8000
+#define INSN_FIELD_ZIMM5 0xf8000
 #define INSN_FIELD_ZIMM10 0x3ff00000
 #define INSN_FIELD_ZIMM11 0x7ff00000
+#define INSN_FIELD_ZIMM6HI 0x4000000
+#define INSN_FIELD_ZIMM6LO 0xf8000
 #define INSN_FIELD_C_NZUIMM10 0x1fe0
 #define INSN_FIELD_C_UIMM7LO 0x60
 #define INSN_FIELD_C_UIMM7HI 0x1c00
@@ -3636,6 +3651,7 @@ DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
 DECLARE_INSN(fclass_h, MATCH_FCLASS_H, MASK_FCLASS_H)
 DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q)
 DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
+DECLARE_INSN(fcvt_bf16_s, MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S)
 DECLARE_INSN(fcvt_d_h, MATCH_FCVT_D_H, MASK_FCVT_D_H)
 DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
 DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
@@ -3665,6 +3681,7 @@ DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
 DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S)
 DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W)
 DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)
+DECLARE_INSN(fcvt_s_bf16, MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16)
 DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
 DECLARE_INSN(fcvt_s_h, MATCH_FCVT_S_H, MASK_FCVT_S_H)
 DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
@@ -4343,6 +4360,7 @@ DECLARE_INSN(vfncvt_rtz_x_f_w, MATCH_VFNCVT_RTZ_X_F_W, MASK_VFNCVT_RTZ_X_F_W)
 DECLARE_INSN(vfncvt_rtz_xu_f_w, MATCH_VFNCVT_RTZ_XU_F_W, MASK_VFNCVT_RTZ_XU_F_W)
 DECLARE_INSN(vfncvt_x_f_w, MATCH_VFNCVT_X_F_W, MASK_VFNCVT_X_F_W)
 DECLARE_INSN(vfncvt_xu_f_w, MATCH_VFNCVT_XU_F_W, MASK_VFNCVT_XU_F_W)
+DECLARE_INSN(vfncvtbf16_f_f_w, MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W)
 DECLARE_INSN(vfnmacc_vf, MATCH_VFNMACC_VF, MASK_VFNMACC_VF)
 DECLARE_INSN(vfnmacc_vv, MATCH_VFNMACC_VV, MASK_VFNMACC_VV)
 DECLARE_INSN(vfnmadd_vf, MATCH_VFNMADD_VF, MASK_VFNMADD_VF)
@@ -4381,8 +4399,11 @@ DECLARE_INSN(vfwcvt_rtz_x_f_v, MATCH_VFWCVT_RTZ_X_F_V, MASK_VFWCVT_RTZ_X_F_V)
 DECLARE_INSN(vfwcvt_rtz_xu_f_v, MATCH_VFWCVT_RTZ_XU_F_V, MASK_VFWCVT_RTZ_XU_F_V)
 DECLARE_INSN(vfwcvt_x_f_v, MATCH_VFWCVT_X_F_V, MASK_VFWCVT_X_F_V)
 DECLARE_INSN(vfwcvt_xu_f_v, MATCH_VFWCVT_XU_F_V, MASK_VFWCVT_XU_F_V)
+DECLARE_INSN(vfwcvtbf16_f_f_v, MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V)
 DECLARE_INSN(vfwmacc_vf, MATCH_VFWMACC_VF, MASK_VFWMACC_VF)
 DECLARE_INSN(vfwmacc_vv, MATCH_VFWMACC_VV, MASK_VFWMACC_VV)
+DECLARE_INSN(vfwmaccbf16_vf, MATCH_VFWMACCBF16_VF, MASK_VFWMACCBF16_VF)
+DECLARE_INSN(vfwmaccbf16_vv, MATCH_VFWMACCBF16_VV, MASK_VFWMACCBF16_VV)
 DECLARE_INSN(vfwmsac_vf, MATCH_VFWMSAC_VF, MASK_VFWMSAC_VF)
 DECLARE_INSN(vfwmsac_vv, MATCH_VFWMSAC_VV, MASK_VFWMSAC_VV)
 DECLARE_INSN(vfwmul_vf, MATCH_VFWMUL_VF, MASK_VFWMUL_VF)