[sim,xcc] Added first few Hauser FP insns (sign-injection)

Also updated FPmove test case to test negation and moving between FP regs

riscv/decode.h

@@ -1,6 +1,7 @@
 #ifndef _RISCV_DECODE_H
 #define _RISCV_DECODE_H
 
+#define __STDC_LIMIT_MACROS
 #include <stdint.h>
 typedef int int128_t __attribute__((mode(TI)));
 typedef unsigned int uint128_t __attribute__((mode(TI)));

riscv/execute.h

@@ -67,72 +67,84 @@ switch((insn.bits >> 0x19) & 0x7f)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe007c00) == 0xd0000000)
+        if((insn.bits & 0xfe007fe0) == 0xd0000ca0)
         {
-          #include "insns/add_fmt.h"
+          #include "insns/sgninj_d.h"
           break;
         }
-        #include "insns/unimp.h"
-      }
-      case 0x1:
+        if((insn.bits & 0xfe007fe0) == 0xd00000a0)
         {
-        if((insn.bits & 0xfe007c00) == 0xd0001000)
-        {
-          #include "insns/sub_fmt.h"
+          #include "insns/sgninj_s.h"
           break;
         }
-        #include "insns/unimp.h"
-      }
-      case 0x2:
+        if((insn.bits & 0xfe007fe0) == 0xd0000000)
         {
-        if((insn.bits & 0xfe007c00) == 0xd0002000)
-        {
-          #include "insns/mul_fmt.h"
+          #include "insns/add_s.h"
           break;
         }
-        #include "insns/unimp.h"
-      }
-      case 0x3:
-      {
-        if((insn.bits & 0xfe007c00) == 0xd0003000)
+        if((insn.bits & 0xfe007fe0) == 0xd0000c00)
         {
-          #include "insns/div_fmt.h"
+          #include "insns/add_d.h"
           break;
         }
-        #include "insns/unimp.h"
+        if((insn.bits & 0xfe007fe0) == 0xd0000ce0)
+        {
+          #include "insns/sgnmul_d.h"
+          break;
         }
-      case 0x4:
+        if((insn.bits & 0xfe007fe0) == 0xd0000cc0)
         {
-        if((insn.bits & 0xfe0ffc00) == 0xd0004000)
+          #include "insns/sgninjn_d.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xd00000c0)
         {
-          #include "insns/sqrt_fmt.h"
+          #include "insns/sgninjn_s.h"
           break;
         }
-        #include "insns/unimp.h"
+        if((insn.bits & 0xfe007fe0) == 0xd0000c40)
+        {
+          #include "insns/mul_d.h"
+          break;
         }
-      case 0x5:
+        if((insn.bits & 0xfe007fe0) == 0xd0000020)
         {
-        if((insn.bits & 0xfe0ffc00) == 0xd0005000)
+          #include "insns/sub_s.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xd0000c20)
         {
-          #include "insns/abs_fmt.h"
+          #include "insns/sub_d.h"
           break;
         }
-        #include "insns/unimp.h"
+        if((insn.bits & 0xfe0fffe0) == 0xd0000080)
+        {
+          #include "insns/sqrt_s.h"
+          break;
         }
-      case 0x6:
+        if((insn.bits & 0xfe0fffe0) == 0xd0000c80)
         {
-        if((insn.bits & 0xfe0ffc00) == 0xd0006000)
+          #include "insns/sqrt_d.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xd00000e0)
         {
-          #include "insns/mov_fmt.h"
+          #include "insns/sgnmul_s.h"
           break;
         }
-        #include "insns/unimp.h"
+        if((insn.bits & 0xfe007fe0) == 0xd0000c60)
+        {
+          #include "insns/div_d.h"
+          break;
         }
-      case 0x7:
+        if((insn.bits & 0xfe007fe0) == 0xd0000060)
         {
-        if((insn.bits & 0xfe0ffc00) == 0xd0007000)
+          #include "insns/div_s.h"
+          break;
+        }
+        if((insn.bits & 0xfe007fe0) == 0xd0000040)
         {
-          #include "insns/neg_fmt.h"
+          #include "insns/mul_s.h"
           break;
         }
         #include "insns/unimp.h"

riscv/insns/mov_fmt.h

@@ -1,2 +0,0 @@
-require_fp;
-FRC = FRA;

riscv/insns/movn.h

@@ -1 +0,0 @@
-if(RB) RC = RA;

riscv/insns/movz.h

@@ -1 +0,0 @@
-if(!RB) RC = RA;

riscv/insns/sgninj_d.h

@@ -0,0 +1,2 @@
+require_fp;
+FRC.bits = (FRA.bits &~ INT64_MIN) | (FRB.bits & INT64_MIN);

riscv/insns/sgninj_s.h

@@ -0,0 +1,2 @@
+require_fp;
+FRC.bits = (FRA.bits &~ (uint32_t)INT32_MIN) | (FRB.bits & (uint32_t)INT32_MIN);

riscv/insns/sgninjn_d.h

@@ -0,0 +1,2 @@
+require_fp;
+FRC.bits = (FRA.bits &~ INT64_MIN) | ((~FRB.bits) & INT64_MIN);

riscv/insns/sgninjn_s.h

@@ -0,0 +1,2 @@
+require_fp;
+FRC.bits = (FRA.bits &~ (uint32_t)INT32_MIN) | ((~FRB.bits) & (uint32_t)INT32_MIN);

riscv/insns/sgnmul_d.h

@@ -0,0 +1,2 @@
+require_fp;
+FRC.bits = FRA.bits ^ (FRB.bits & INT64_MIN);

riscv/insns/sgnmul_s.h

@@ -0,0 +1,2 @@
+require_fp;
+FRC.bits = FRA.bits ^ (FRB.bits & (uint32_t)INT32_MIN);