From c04d2381d19e34077aab9b8a7625438f3e0f785a Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Tue, 5 Aug 2025 22:52:47 -0700
Subject: [PATCH] Remove dead code in vector unit

---
 riscv/vector_unit.cc | 4 ----
 riscv/vector_unit.h  | 4 ----
 2 files changed, 8 deletions(-)

diff --git a/riscv/vector_unit.cc b/riscv/vector_unit.cc
index ad0f23f5..b4ef6404 100644
--- a/riscv/vector_unit.cc
+++ b/riscv/vector_unit.cc
@@ -76,7 +76,6 @@ reg_t vectorUnit_t::vectorUnit_t::set_vl(int rd, int rs1, reg_t reqVL, reg_t new
   }
 
   vstart->write_raw(0);
-  setvl_count++;
   return vl->read();
 }
 
@@ -91,7 +90,6 @@ template<class T> T& vectorUnit_t::elt(reg_t vReg, reg_t n, bool UNUSED is_write
   // bits when changing SEW, thus we need to index from the end on BE.
   n ^= elts_per_reg - 1;
 #endif
-  reg_referenced[vReg] = 1;
 
   if (unlikely(p->get_log_commits_enabled() && is_write))
     p->get_state()->log_reg_write[((vReg) << 4) | 2] = {0, 0};
@@ -140,8 +138,6 @@ vectorUnit_t::elt_group(reg_t vReg, reg_t n, bool UNUSED is_write) {
 
   // Element groups per register groups
   for (reg_t vidx = reg_first; vidx <= reg_last; ++vidx) {
-      reg_referenced[vidx] = 1;
-
       if (unlikely(p->get_log_commits_enabled() && is_write)) {
           p->get_state()->log_reg_write[(vidx << 4) | 2] = {0, 0};
       }
diff --git a/riscv/vector_unit.h b/riscv/vector_unit.h
index 104ef1d4..02456391 100644
--- a/riscv/vector_unit.h
+++ b/riscv/vector_unit.h
@@ -89,8 +89,6 @@ class vectorUnit_t
 public:
   processor_t* p;
   void *reg_file;
-  char reg_referenced[NVPR];
-  int setvl_count;
   reg_t vlmax;
   reg_t vlenb;
   csr_t_p vxsat;
@@ -127,8 +125,6 @@ public:
   vectorUnit_t():
     p(0),
     reg_file(0),
-    reg_referenced{0},
-    setvl_count(0),
     vlmax(0),
     vlenb(0),
     vxsat(0),