rvv: remove quad instructions

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

riscv/encoding.h

@@ -1414,14 +1414,6 @@
 #define MASK_VNCLIPU_WX  0xfc00707f
 #define MATCH_VNCLIP_WX 0xbc004057
 #define MASK_VNCLIP_WX  0xfc00707f
-#define MATCH_VQMACCU_VX 0xf0004057
-#define MASK_VQMACCU_VX  0xfc00707f
-#define MATCH_VQMACC_VX 0xf4004057
-#define MASK_VQMACC_VX  0xfc00707f
-#define MATCH_VQMACCUS_VX 0xf8004057
-#define MASK_VQMACCUS_VX  0xfc00707f
-#define MATCH_VQMACCSU_VX 0xfc004057
-#define MASK_VQMACCSU_VX  0xfc00707f
 #define MATCH_VADD_VV 0x57
 #define MASK_VADD_VV  0xfc00707f
 #define MATCH_VSUB_VV 0x8000057
@@ -2710,10 +2702,6 @@ DECLARE_INSN(vnsrl_wx, MATCH_VNSRL_WX, MASK_VNSRL_WX)
 DECLARE_INSN(vnsra_wx, MATCH_VNSRA_WX, MASK_VNSRA_WX)
 DECLARE_INSN(vnclipu_wx, MATCH_VNCLIPU_WX, MASK_VNCLIPU_WX)
 DECLARE_INSN(vnclip_wx, MATCH_VNCLIP_WX, MASK_VNCLIP_WX)
-DECLARE_INSN(vqmaccu_vx, MATCH_VQMACCU_VX, MASK_VQMACCU_VX)
-DECLARE_INSN(vqmacc_vx, MATCH_VQMACC_VX, MASK_VQMACC_VX)
-DECLARE_INSN(vqmaccus_vx, MATCH_VQMACCUS_VX, MASK_VQMACCUS_VX)
-DECLARE_INSN(vqmaccsu_vx, MATCH_VQMACCSU_VX, MASK_VQMACCSU_VX)
 DECLARE_INSN(vadd_vv, MATCH_VADD_VV, MASK_VADD_VV)
 DECLARE_INSN(vsub_vv, MATCH_VSUB_VV, MASK_VSUB_VV)
 DECLARE_INSN(vminu_vv, MATCH_VMINU_VV, MASK_VMINU_VV)

riscv/insns/vqmacc_vv.h

@@ -1,5 +0,0 @@
-// vqsmacc.vv vd, vs2, vs1
-VI_VV_LOOP_QUAD
-({
-  VI_QUAD_OP_AND_ASSIGN(vs2, vs1, vd_w, *, +, int);
-})

riscv/insns/vqmacc_vx.h

@@ -1,5 +0,0 @@
-// vqmacc.vx vd, vs2, rs1
-VI_VX_LOOP_QUAD
-({
-  VI_QUAD_OP_AND_ASSIGN(vs2, rs1, vd_w, *, +, int);
-})

riscv/insns/vqmaccsu_vv.h

@@ -1,5 +0,0 @@
-// vqmaccsu.vx vd, vs2, rs1
-VI_VV_LOOP_QUAD
-({
-  VI_QUAD_OP_AND_ASSIGN_MIX(vs2, vs1, vd_w, *, +, int, uint, int);
-})

riscv/insns/vqmaccsu_vx.h

@@ -1,5 +0,0 @@
-// vqmaccsu.vx vd, vs2, rs1
-VI_VX_LOOP_QUAD
-({
-  VI_QUAD_OP_AND_ASSIGN_MIX(vs2, rs1, vd_w, *, +, int, uint, int);
-})

riscv/insns/vqmaccu_vv.h

@@ -1,5 +0,0 @@
-// vqmaccu.vv vd, vs2, vs1
-VI_VV_LOOP_QUAD
-({
-  VI_QUAD_OP_AND_ASSIGN(vs2, vs1, vd_w, *, +, uint);
-})

riscv/insns/vqmaccu_vx.h

@@ -1,5 +0,0 @@
-// vqmaccu.vx vd, vs2, rs1
-VI_VX_LOOP_QUAD
-({
-  VI_QUAD_OP_AND_ASSIGN(vs2, rs1, vd_w, *, +, uint);
-})

riscv/insns/vqmaccus_vx.h

@@ -1,5 +0,0 @@
-// vqmaccus.vx  vd, vs2, rs1
-VI_VX_LOOP_QUAD
-({
-  VI_QUAD_OP_AND_ASSIGN_MIX(vs2, rs1, vd_w, *, +, int, int, uint);
-})

riscv/processor.cc

@@ -264,8 +264,6 @@ void processor_t::parse_isa_string(const char* str)
       auto ext_str = std::string(ext, end - ext);
       if (ext_str == "zfh") {
         extension_table[EXT_ZFH] = true;
-      } else if (ext_str == "zvqmac") {
-        extension_table[EXT_ZVQMAC] = true;
       } else {
         sprintf(error_msg, "unsupported extension '%s'", ext_str.c_str());
         bad_isa_string(str, error_msg);
@@ -291,9 +289,6 @@ void processor_t::parse_isa_string(const char* str)
 
   if (supports_extension('Q') && !supports_extension('D'))
     bad_isa_string(str, "'Q' extension requires 'D'");
-
-  if (supports_extension(EXT_ZVQMAC) && !supports_extension('V'))
-    bad_isa_string(str, "'Zvqmac' extension requires 'V'");
 }
 
 void state_t::reset(reg_t max_isa)

riscv/processor.h

@@ -247,7 +247,6 @@ typedef enum {
   // 65('A') ~ 90('Z') is reserved for standard isa in misa
   EXT_ZFH   = 0,
   EXT_ZVEDIV,
-  EXT_ZVQMAC,
 } isa_extension_t;
 
 // Count number of contiguous 1 bits starting from the LSB.

riscv/riscv.mk.in

@@ -450,13 +450,6 @@ riscv_insn_ext_v_alu_int = \
 	vor_vi \
 	vor_vv \
 	vor_vx \
-	vqmacc_vv \
-	vqmacc_vx \
-	vqmaccsu_vv \
-	vqmaccsu_vx \
-	vqmaccu_vv \
-	vqmaccu_vx \
-	vqmaccus_vx \
 	vredand_vs \
 	vredmax_vs \
 	vredmaxu_vs \

spike_main/disasm.cc

@@ -950,10 +950,6 @@ disassembler_t::disassembler_t(int xlen)
   DISASM_OPIV_S___INSN(vwredsum,  1);
   DISASM_OPIV_V___INSN(vdotu,     0);
   DISASM_OPIV_V___INSN(vdot,      1);
-  DISASM_OPIV_VX__INSN(vqmaccu,   0);
-  DISASM_OPIV_VX__INSN(vqmacc,    1);
-  DISASM_OPIV__X__INSN(vqmaccus,  1);
-  DISASM_OPIV_VX__INSN(vqmaccsu,  0);
 
   //OPMVV/OPMVX
   //0b00_0000