From 3676772fd0fee2eb94a55f4d42dbf5eeabd003f4 Mon Sep 17 00:00:00 2001
From: Quan Nguyen <quannguyen@berkeley.edu>
Date: Thu, 17 Oct 2013 23:47:14 -0700
Subject: [PATCH 1/7] Add empty opcode header files for half-precision

* Update riscv/opcodes.h through the riscv-opcodes repository.
---
 riscv/insns/fadd_h.h    |  0
 riscv/insns/fcvt_d_h.h  |  0
 riscv/insns/fcvt_h_d.h  |  0
 riscv/insns/fcvt_h_l.h  |  0
 riscv/insns/fcvt_h_lu.h |  0
 riscv/insns/fcvt_h_s.h  |  0
 riscv/insns/fcvt_h_w.h  |  0
 riscv/insns/fcvt_h_wu.h |  0
 riscv/insns/fcvt_l_h.h  |  0
 riscv/insns/fcvt_lu_h.h |  0
 riscv/insns/fcvt_s_h.h  |  0
 riscv/insns/fcvt_w_h.h  |  0
 riscv/insns/fcvt_wu_h.h |  0
 riscv/insns/fdiv_h.h    |  0
 riscv/insns/feq_h.h     |  0
 riscv/insns/fle_h.h     |  0
 riscv/insns/flh.h       |  0
 riscv/insns/flt_h.h     |  0
 riscv/insns/fmadd_h.h   |  0
 riscv/insns/fmax_h.h    |  0
 riscv/insns/fmin_h.h    |  0
 riscv/insns/fmsub_h.h   |  0
 riscv/insns/fmul_h.h    |  0
 riscv/insns/fmv_h_x.h   |  0
 riscv/insns/fmv_x_h.h   |  0
 riscv/insns/fnmadd_h.h  |  0
 riscv/insns/fnmsub_h.h  |  0
 riscv/insns/fsgnj_h.h   |  0
 riscv/insns/fsgnjn_h.h  |  0
 riscv/insns/fsgnjx_h.h  |  0
 riscv/insns/fsh.h       |  0
 riscv/insns/fsqrt_h.h   |  0
 riscv/insns/fsub_h.h    |  0
 riscv/opcodes.h         | 41 +++++++++++++++++++++++++++++++++++++----
 34 files changed, 37 insertions(+), 4 deletions(-)
 create mode 100644 riscv/insns/fadd_h.h
 create mode 100644 riscv/insns/fcvt_d_h.h
 create mode 100644 riscv/insns/fcvt_h_d.h
 create mode 100644 riscv/insns/fcvt_h_l.h
 create mode 100644 riscv/insns/fcvt_h_lu.h
 create mode 100644 riscv/insns/fcvt_h_s.h
 create mode 100644 riscv/insns/fcvt_h_w.h
 create mode 100644 riscv/insns/fcvt_h_wu.h
 create mode 100644 riscv/insns/fcvt_l_h.h
 create mode 100644 riscv/insns/fcvt_lu_h.h
 create mode 100644 riscv/insns/fcvt_s_h.h
 create mode 100644 riscv/insns/fcvt_w_h.h
 create mode 100644 riscv/insns/fcvt_wu_h.h
 create mode 100644 riscv/insns/fdiv_h.h
 create mode 100644 riscv/insns/feq_h.h
 create mode 100644 riscv/insns/fle_h.h
 create mode 100644 riscv/insns/flh.h
 create mode 100644 riscv/insns/flt_h.h
 create mode 100644 riscv/insns/fmadd_h.h
 create mode 100644 riscv/insns/fmax_h.h
 create mode 100644 riscv/insns/fmin_h.h
 create mode 100644 riscv/insns/fmsub_h.h
 create mode 100644 riscv/insns/fmul_h.h
 create mode 100644 riscv/insns/fmv_h_x.h
 create mode 100644 riscv/insns/fmv_x_h.h
 create mode 100644 riscv/insns/fnmadd_h.h
 create mode 100644 riscv/insns/fnmsub_h.h
 create mode 100644 riscv/insns/fsgnj_h.h
 create mode 100644 riscv/insns/fsgnjn_h.h
 create mode 100644 riscv/insns/fsgnjx_h.h
 create mode 100644 riscv/insns/fsh.h
 create mode 100644 riscv/insns/fsqrt_h.h
 create mode 100644 riscv/insns/fsub_h.h

diff --git a/riscv/insns/fadd_h.h b/riscv/insns/fadd_h.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fcvt_d_h.h b/riscv/insns/fcvt_d_h.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fcvt_h_d.h b/riscv/insns/fcvt_h_d.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fcvt_h_l.h b/riscv/insns/fcvt_h_l.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fcvt_h_lu.h b/riscv/insns/fcvt_h_lu.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fcvt_h_s.h b/riscv/insns/fcvt_h_s.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fcvt_h_w.h b/riscv/insns/fcvt_h_w.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fcvt_h_wu.h b/riscv/insns/fcvt_h_wu.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fcvt_l_h.h b/riscv/insns/fcvt_l_h.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fcvt_lu_h.h b/riscv/insns/fcvt_lu_h.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fcvt_s_h.h b/riscv/insns/fcvt_s_h.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fcvt_w_h.h b/riscv/insns/fcvt_w_h.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fcvt_wu_h.h b/riscv/insns/fcvt_wu_h.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fdiv_h.h b/riscv/insns/fdiv_h.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/feq_h.h b/riscv/insns/feq_h.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fle_h.h b/riscv/insns/fle_h.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/flh.h b/riscv/insns/flh.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/flt_h.h b/riscv/insns/flt_h.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fmadd_h.h b/riscv/insns/fmadd_h.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fmax_h.h b/riscv/insns/fmax_h.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fmin_h.h b/riscv/insns/fmin_h.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fmsub_h.h b/riscv/insns/fmsub_h.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fmul_h.h b/riscv/insns/fmul_h.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fmv_h_x.h b/riscv/insns/fmv_h_x.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fmv_x_h.h b/riscv/insns/fmv_x_h.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fnmadd_h.h b/riscv/insns/fnmadd_h.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fnmsub_h.h b/riscv/insns/fnmsub_h.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fsgnj_h.h b/riscv/insns/fsgnj_h.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fsgnjn_h.h b/riscv/insns/fsgnjn_h.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fsgnjx_h.h b/riscv/insns/fsgnjx_h.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fsh.h b/riscv/insns/fsh.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fsqrt_h.h b/riscv/insns/fsqrt_h.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/insns/fsub_h.h b/riscv/insns/fsub_h.h
new file mode 100644
index 00000000..e69de29b
diff --git a/riscv/opcodes.h b/riscv/opcodes.h
index 2a42554c..0ee6776c 100644
--- a/riscv/opcodes.h
+++ b/riscv/opcodes.h
@@ -1,5 +1,7 @@
 DECLARE_INSN(fmv_s_x, 0xf0000053, 0xfff0707f)
+DECLARE_INSN(fmin_h, 0xc4000053, 0xfe00707f)
 DECLARE_INSN(amoxor_w, 0x2000202f, 0xf800707f)
+DECLARE_INSN(fmv_d_x, 0xf2000053, 0xfff0707f)
 DECLARE_INSN(remuw, 0x200703b, 0xfe00707f)
 DECLARE_INSN(fmin_d, 0xc2000053, 0xfe00707f)
 DECLARE_INSN(amomax_d, 0xa000302f, 0xf800707f)
@@ -10,7 +12,7 @@ DECLARE_INSN(lb, 0x3, 0x707f)
 DECLARE_INSN(fcvt_s_wu, 0x78000053, 0xfff0007f)
 DECLARE_INSN(fcvt_d_l, 0x62000053, 0xfff0007f)
 DECLARE_INSN(lh, 0x1003, 0x707f)
-DECLARE_INSN(frsr, 0xe8000053, 0xfffff07f)
+DECLARE_INSN(fcvt_d_h, 0x8c000053, 0xfff0007f)
 DECLARE_INSN(fcvt_d_w, 0x72000053, 0xfff0007f)
 DECLARE_INSN(lw, 0x2003, 0x707f)
 DECLARE_INSN(add, 0x33, 0xfe00707f)
@@ -24,22 +26,30 @@ DECLARE_INSN(bgeu, 0x7063, 0x707f)
 DECLARE_INSN(fadd_d, 0x2000053, 0xfe00007f)
 DECLARE_INSN(sltiu, 0x3013, 0x707f)
 DECLARE_INSN(mtpcr, 0x73, 0xfe00707f)
+DECLARE_INSN(fadd_h, 0x4000053, 0xfe00007f)
+DECLARE_INSN(fcvt_s_h, 0x84000053, 0xfff0007f)
 DECLARE_INSN(break, 0x1077, 0xffffffff)
 DECLARE_INSN(fcvt_s_w, 0x70000053, 0xfff0007f)
 DECLARE_INSN(mul, 0x2000033, 0xfe00707f)
+DECLARE_INSN(fcvt_w_h, 0x54000053, 0xfff0007f)
 DECLARE_INSN(amominu_d, 0xc000302f, 0xf800707f)
 DECLARE_INSN(srli, 0x5013, 0xfc00707f)
+DECLARE_INSN(fnmadd_h, 0x400004f, 0x600007f)
 DECLARE_INSN(amominu_w, 0xc000202f, 0xf800707f)
 DECLARE_INSN(divuw, 0x200503b, 0xfe00707f)
 DECLARE_INSN(mulw, 0x200003b, 0xfe00707f)
 DECLARE_INSN(srlw, 0x503b, 0xfe00707f)
 DECLARE_INSN(div, 0x2004033, 0xfe00707f)
+DECLARE_INSN(fmv_h_x, 0xf4000053, 0xfff0707f)
 DECLARE_INSN(fdiv_d, 0x1a000053, 0xfe00007f)
 DECLARE_INSN(fence, 0xf, 0x707f)
 DECLARE_INSN(fnmsub_s, 0x4b, 0x600007f)
 DECLARE_INSN(fcvt_l_s, 0x40000053, 0xfff0007f)
-DECLARE_INSN(fle_s, 0xb8000053, 0xfe00707f)
+DECLARE_INSN(fdiv_h, 0x1c000053, 0xfe00007f)
+DECLARE_INSN(fcvt_h_wu, 0x7c000053, 0xfff0007f)
+DECLARE_INSN(fnmsub_h, 0x400004b, 0x600007f)
 DECLARE_INSN(fdiv_s, 0x18000053, 0xfe00007f)
+DECLARE_INSN(fcvt_l_h, 0x44000053, 0xfff0007f)
 DECLARE_INSN(fle_d, 0xba000053, 0xfe00707f)
 DECLARE_INSN(fence_i, 0x100f, 0x707f)
 DECLARE_INSN(fnmsub_d, 0x200004b, 0x600007f)
@@ -48,13 +58,17 @@ DECLARE_INSN(sll, 0x1033, 0xfe00707f)
 DECLARE_INSN(xor, 0x4033, 0xfe00707f)
 DECLARE_INSN(sub, 0x40000033, 0xfe00707f)
 DECLARE_INSN(eret, 0x4073, 0xffffffff)
+DECLARE_INSN(fcvt_h_s, 0x90000053, 0xfff0007f)
 DECLARE_INSN(blt, 0x4063, 0x707f)
+DECLARE_INSN(fcvt_h_w, 0x74000053, 0xfff0007f)
 DECLARE_INSN(sc_w, 0x1800202f, 0xf800707f)
 DECLARE_INSN(rem, 0x2006033, 0xfe00707f)
 DECLARE_INSN(srliw, 0x501b, 0xfe00707f)
 DECLARE_INSN(lui, 0x37, 0x7f)
 DECLARE_INSN(fcvt_s_lu, 0x68000053, 0xfff0007f)
 DECLARE_INSN(addi, 0x13, 0x707f)
+DECLARE_INSN(fcvt_h_d, 0x92000053, 0xfff0007f)
+DECLARE_INSN(flt_h, 0xb4000053, 0xfe00707f)
 DECLARE_INSN(mulh, 0x2001033, 0xfe00707f)
 DECLARE_INSN(fmul_s, 0x10000053, 0xfe00007f)
 DECLARE_INSN(srai, 0x40005013, 0xfc00707f)
@@ -64,6 +78,7 @@ DECLARE_INSN(sraw, 0x4000503b, 0xfe00707f)
 DECLARE_INSN(fmul_d, 0x12000053, 0xfe00007f)
 DECLARE_INSN(ld, 0x3003, 0x707f)
 DECLARE_INSN(ori, 0x6013, 0x707f)
+DECLARE_INSN(fmul_h, 0x14000053, 0xfe00007f)
 DECLARE_INSN(flt_s, 0xb0000053, 0xfe00707f)
 DECLARE_INSN(addiw, 0x1b, 0x707f)
 DECLARE_INSN(amoand_w, 0x6000202f, 0xf800707f)
@@ -77,26 +92,31 @@ DECLARE_INSN(fsub_d, 0xa000053, 0xfe00007f)
 DECLARE_INSN(fsgnjx_s, 0x38000053, 0xfe00707f)
 DECLARE_INSN(feq_d, 0xaa000053, 0xfe00707f)
 DECLARE_INSN(fcvt_d_wu, 0x7a000053, 0xfff0007f)
+DECLARE_INSN(feq_h, 0xac000053, 0xfe00707f)
 DECLARE_INSN(or, 0x6033, 0xfe00707f)
 DECLARE_INSN(rdinstret, 0x4004077, 0xfffff07f)
 DECLARE_INSN(fcvt_wu_d, 0x5a000053, 0xfff0007f)
 DECLARE_INSN(subw, 0x4000003b, 0xfe00707f)
 DECLARE_INSN(fmax_s, 0xc8000053, 0xfe00707f)
 DECLARE_INSN(amomaxu_d, 0xe000302f, 0xf800707f)
+DECLARE_INSN(fcvt_wu_h, 0x5c000053, 0xfff0007f)
 DECLARE_INSN(xori, 0x4013, 0x707f)
 DECLARE_INSN(amoxor_d, 0x2000302f, 0xf800707f)
 DECLARE_INSN(amomaxu_w, 0xe000202f, 0xf800707f)
 DECLARE_INSN(fcvt_wu_s, 0x58000053, 0xfff0007f)
+DECLARE_INSN(frsr, 0xe8000053, 0xfffff07f)
+DECLARE_INSN(fmax_h, 0xcc000053, 0xfe00707f)
 DECLARE_INSN(rdtime, 0x2004077, 0xfffff07f)
 DECLARE_INSN(andi, 0x7013, 0x707f)
 DECLARE_INSN(clearpcr, 0x3073, 0x707f)
+DECLARE_INSN(fmadd_h, 0x4000043, 0x600007f)
 DECLARE_INSN(fmv_x_s, 0xe0000053, 0xfff0707f)
 DECLARE_INSN(fsgnjn_d, 0x32000053, 0xfe00707f)
 DECLARE_INSN(fnmadd_s, 0x4f, 0x600007f)
 DECLARE_INSN(jal, 0x67, 0x7f)
 DECLARE_INSN(lwu, 0x6003, 0x707f)
 DECLARE_INSN(fmv_x_d, 0xe2000053, 0xfff0707f)
-DECLARE_INSN(fnmadd_d, 0x200004f, 0x600007f)
+DECLARE_INSN(fmv_x_h, 0xe4000053, 0xfff0707f)
 DECLARE_INSN(amoadd_d, 0x302f, 0xf800707f)
 DECLARE_INSN(lr_d, 0x1000302f, 0xf9f0707f)
 DECLARE_INSN(fcvt_w_s, 0x50000053, 0xfff0007f)
@@ -104,8 +124,11 @@ DECLARE_INSN(mulhsu, 0x2002033, 0xfe00707f)
 DECLARE_INSN(amoadd_w, 0x202f, 0xf800707f)
 DECLARE_INSN(fcvt_d_lu, 0x6a000053, 0xfff0007f)
 DECLARE_INSN(lr_w, 0x1000202f, 0xf9f0707f)
+DECLARE_INSN(fcvt_h_l, 0x64000053, 0xfff0007f)
 DECLARE_INSN(fcvt_w_d, 0x52000053, 0xfff0007f)
+DECLARE_INSN(fsub_h, 0xc000053, 0xfe00007f)
 DECLARE_INSN(slt, 0x2033, 0xfe00707f)
+DECLARE_INSN(fnmadd_d, 0x200004f, 0x600007f)
 DECLARE_INSN(sllw, 0x103b, 0xfe00707f)
 DECLARE_INSN(amoor_d, 0x4000302f, 0xf800707f)
 DECLARE_INSN(slti, 0x2013, 0x707f)
@@ -113,16 +136,21 @@ DECLARE_INSN(remu, 0x2007033, 0xfe00707f)
 DECLARE_INSN(flw, 0x2007, 0x707f)
 DECLARE_INSN(remw, 0x200603b, 0xfe00707f)
 DECLARE_INSN(sltu, 0x3033, 0xfe00707f)
+DECLARE_INSN(flh, 0x1007, 0x707f)
 DECLARE_INSN(slli, 0x40001013, 0xfc00707f)
 DECLARE_INSN(amoor_w, 0x4000202f, 0xf800707f)
+DECLARE_INSN(fle_h, 0xbc000053, 0xfe00707f)
 DECLARE_INSN(beq, 0x63, 0x707f)
 DECLARE_INSN(fld, 0x3007, 0x707f)
 DECLARE_INSN(fsub_s, 0x8000053, 0xfe00007f)
 DECLARE_INSN(and, 0x7033, 0xfe00707f)
-DECLARE_INSN(fmv_d_x, 0xf2000053, 0xfff0707f)
+DECLARE_INSN(fcvt_h_lu, 0x6c000053, 0xfff0007f)
 DECLARE_INSN(lbu, 0x4003, 0x707f)
 DECLARE_INSN(syscall, 0x77, 0xffffffff)
 DECLARE_INSN(fsgnj_s, 0x28000053, 0xfe00707f)
+DECLARE_INSN(fle_s, 0xb8000053, 0xfe00707f)
+DECLARE_INSN(fsgnj_h, 0x2c000053, 0xfe00707f)
+DECLARE_INSN(fsgnjx_h, 0x3c000053, 0xfe00707f)
 DECLARE_INSN(amomax_w, 0xa000202f, 0xf800707f)
 DECLARE_INSN(fsgnj_d, 0x2a000053, 0xfe00707f)
 DECLARE_INSN(mulhu, 0x2003033, 0xfe00707f)
@@ -139,19 +167,24 @@ DECLARE_INSN(fsqrt_s, 0x20000053, 0xfff0007f)
 DECLARE_INSN(amomin_w, 0x8000202f, 0xf800707f)
 DECLARE_INSN(fsgnjn_s, 0x30000053, 0xfe00707f)
 DECLARE_INSN(amoswap_d, 0x800302f, 0xf800707f)
+DECLARE_INSN(fsgnjn_h, 0x34000053, 0xfe00707f)
 DECLARE_INSN(fsqrt_d, 0x22000053, 0xfff0007f)
 DECLARE_INSN(fmadd_d, 0x2000043, 0x600007f)
 DECLARE_INSN(divw, 0x200403b, 0xfe00707f)
 DECLARE_INSN(amomin_d, 0x8000302f, 0xf800707f)
 DECLARE_INSN(divu, 0x2005033, 0xfe00707f)
 DECLARE_INSN(amoswap_w, 0x800202f, 0xf800707f)
+DECLARE_INSN(fsqrt_h, 0x24000053, 0xfff0007f)
 DECLARE_INSN(jalr, 0x6f, 0x707f)
 DECLARE_INSN(fadd_s, 0x53, 0xfe00007f)
 DECLARE_INSN(fsd, 0x3027, 0x707f)
+DECLARE_INSN(fsh, 0x1027, 0x707f)
 DECLARE_INSN(sw, 0x2023, 0x707f)
 DECLARE_INSN(fmsub_s, 0x47, 0x600007f)
 DECLARE_INSN(lhu, 0x5003, 0x707f)
 DECLARE_INSN(sh, 0x1023, 0x707f)
+DECLARE_INSN(fcvt_lu_h, 0x4c000053, 0xfff0007f)
+DECLARE_INSN(fmsub_h, 0x4000047, 0x600007f)
 DECLARE_INSN(fsw, 0x2027, 0x707f)
 DECLARE_INSN(sb, 0x23, 0x707f)
 DECLARE_INSN(fmsub_d, 0x2000047, 0x600007f)

From 6ca90a89e59946efa7620cf9898fed261309a07f Mon Sep 17 00:00:00 2001
From: Quan Nguyen <quannguyen@berkeley.edu>
Date: Sun, 27 Oct 2013 23:02:23 -0700
Subject: [PATCH 2/7] Add missing fcvt opcodes through riscv-opcodes

---
 riscv/opcodes.h | 41 ++++-------------------------------------
 1 file changed, 4 insertions(+), 37 deletions(-)

diff --git a/riscv/opcodes.h b/riscv/opcodes.h
index 0ee6776c..2a42554c 100644
--- a/riscv/opcodes.h
+++ b/riscv/opcodes.h
@@ -1,7 +1,5 @@
 DECLARE_INSN(fmv_s_x, 0xf0000053, 0xfff0707f)
-DECLARE_INSN(fmin_h, 0xc4000053, 0xfe00707f)
 DECLARE_INSN(amoxor_w, 0x2000202f, 0xf800707f)
-DECLARE_INSN(fmv_d_x, 0xf2000053, 0xfff0707f)
 DECLARE_INSN(remuw, 0x200703b, 0xfe00707f)
 DECLARE_INSN(fmin_d, 0xc2000053, 0xfe00707f)
 DECLARE_INSN(amomax_d, 0xa000302f, 0xf800707f)
@@ -12,7 +10,7 @@ DECLARE_INSN(lb, 0x3, 0x707f)
 DECLARE_INSN(fcvt_s_wu, 0x78000053, 0xfff0007f)
 DECLARE_INSN(fcvt_d_l, 0x62000053, 0xfff0007f)
 DECLARE_INSN(lh, 0x1003, 0x707f)
-DECLARE_INSN(fcvt_d_h, 0x8c000053, 0xfff0007f)
+DECLARE_INSN(frsr, 0xe8000053, 0xfffff07f)
 DECLARE_INSN(fcvt_d_w, 0x72000053, 0xfff0007f)
 DECLARE_INSN(lw, 0x2003, 0x707f)
 DECLARE_INSN(add, 0x33, 0xfe00707f)
@@ -26,30 +24,22 @@ DECLARE_INSN(bgeu, 0x7063, 0x707f)
 DECLARE_INSN(fadd_d, 0x2000053, 0xfe00007f)
 DECLARE_INSN(sltiu, 0x3013, 0x707f)
 DECLARE_INSN(mtpcr, 0x73, 0xfe00707f)
-DECLARE_INSN(fadd_h, 0x4000053, 0xfe00007f)
-DECLARE_INSN(fcvt_s_h, 0x84000053, 0xfff0007f)
 DECLARE_INSN(break, 0x1077, 0xffffffff)
 DECLARE_INSN(fcvt_s_w, 0x70000053, 0xfff0007f)
 DECLARE_INSN(mul, 0x2000033, 0xfe00707f)
-DECLARE_INSN(fcvt_w_h, 0x54000053, 0xfff0007f)
 DECLARE_INSN(amominu_d, 0xc000302f, 0xf800707f)
 DECLARE_INSN(srli, 0x5013, 0xfc00707f)
-DECLARE_INSN(fnmadd_h, 0x400004f, 0x600007f)
 DECLARE_INSN(amominu_w, 0xc000202f, 0xf800707f)
 DECLARE_INSN(divuw, 0x200503b, 0xfe00707f)
 DECLARE_INSN(mulw, 0x200003b, 0xfe00707f)
 DECLARE_INSN(srlw, 0x503b, 0xfe00707f)
 DECLARE_INSN(div, 0x2004033, 0xfe00707f)
-DECLARE_INSN(fmv_h_x, 0xf4000053, 0xfff0707f)
 DECLARE_INSN(fdiv_d, 0x1a000053, 0xfe00007f)
 DECLARE_INSN(fence, 0xf, 0x707f)
 DECLARE_INSN(fnmsub_s, 0x4b, 0x600007f)
 DECLARE_INSN(fcvt_l_s, 0x40000053, 0xfff0007f)
-DECLARE_INSN(fdiv_h, 0x1c000053, 0xfe00007f)
-DECLARE_INSN(fcvt_h_wu, 0x7c000053, 0xfff0007f)
-DECLARE_INSN(fnmsub_h, 0x400004b, 0x600007f)
+DECLARE_INSN(fle_s, 0xb8000053, 0xfe00707f)
 DECLARE_INSN(fdiv_s, 0x18000053, 0xfe00007f)
-DECLARE_INSN(fcvt_l_h, 0x44000053, 0xfff0007f)
 DECLARE_INSN(fle_d, 0xba000053, 0xfe00707f)
 DECLARE_INSN(fence_i, 0x100f, 0x707f)
 DECLARE_INSN(fnmsub_d, 0x200004b, 0x600007f)
@@ -58,17 +48,13 @@ DECLARE_INSN(sll, 0x1033, 0xfe00707f)
 DECLARE_INSN(xor, 0x4033, 0xfe00707f)
 DECLARE_INSN(sub, 0x40000033, 0xfe00707f)
 DECLARE_INSN(eret, 0x4073, 0xffffffff)
-DECLARE_INSN(fcvt_h_s, 0x90000053, 0xfff0007f)
 DECLARE_INSN(blt, 0x4063, 0x707f)
-DECLARE_INSN(fcvt_h_w, 0x74000053, 0xfff0007f)
 DECLARE_INSN(sc_w, 0x1800202f, 0xf800707f)
 DECLARE_INSN(rem, 0x2006033, 0xfe00707f)
 DECLARE_INSN(srliw, 0x501b, 0xfe00707f)
 DECLARE_INSN(lui, 0x37, 0x7f)
 DECLARE_INSN(fcvt_s_lu, 0x68000053, 0xfff0007f)
 DECLARE_INSN(addi, 0x13, 0x707f)
-DECLARE_INSN(fcvt_h_d, 0x92000053, 0xfff0007f)
-DECLARE_INSN(flt_h, 0xb4000053, 0xfe00707f)
 DECLARE_INSN(mulh, 0x2001033, 0xfe00707f)
 DECLARE_INSN(fmul_s, 0x10000053, 0xfe00007f)
 DECLARE_INSN(srai, 0x40005013, 0xfc00707f)
@@ -78,7 +64,6 @@ DECLARE_INSN(sraw, 0x4000503b, 0xfe00707f)
 DECLARE_INSN(fmul_d, 0x12000053, 0xfe00007f)
 DECLARE_INSN(ld, 0x3003, 0x707f)
 DECLARE_INSN(ori, 0x6013, 0x707f)
-DECLARE_INSN(fmul_h, 0x14000053, 0xfe00007f)
 DECLARE_INSN(flt_s, 0xb0000053, 0xfe00707f)
 DECLARE_INSN(addiw, 0x1b, 0x707f)
 DECLARE_INSN(amoand_w, 0x6000202f, 0xf800707f)
@@ -92,31 +77,26 @@ DECLARE_INSN(fsub_d, 0xa000053, 0xfe00007f)
 DECLARE_INSN(fsgnjx_s, 0x38000053, 0xfe00707f)
 DECLARE_INSN(feq_d, 0xaa000053, 0xfe00707f)
 DECLARE_INSN(fcvt_d_wu, 0x7a000053, 0xfff0007f)
-DECLARE_INSN(feq_h, 0xac000053, 0xfe00707f)
 DECLARE_INSN(or, 0x6033, 0xfe00707f)
 DECLARE_INSN(rdinstret, 0x4004077, 0xfffff07f)
 DECLARE_INSN(fcvt_wu_d, 0x5a000053, 0xfff0007f)
 DECLARE_INSN(subw, 0x4000003b, 0xfe00707f)
 DECLARE_INSN(fmax_s, 0xc8000053, 0xfe00707f)
 DECLARE_INSN(amomaxu_d, 0xe000302f, 0xf800707f)
-DECLARE_INSN(fcvt_wu_h, 0x5c000053, 0xfff0007f)
 DECLARE_INSN(xori, 0x4013, 0x707f)
 DECLARE_INSN(amoxor_d, 0x2000302f, 0xf800707f)
 DECLARE_INSN(amomaxu_w, 0xe000202f, 0xf800707f)
 DECLARE_INSN(fcvt_wu_s, 0x58000053, 0xfff0007f)
-DECLARE_INSN(frsr, 0xe8000053, 0xfffff07f)
-DECLARE_INSN(fmax_h, 0xcc000053, 0xfe00707f)
 DECLARE_INSN(rdtime, 0x2004077, 0xfffff07f)
 DECLARE_INSN(andi, 0x7013, 0x707f)
 DECLARE_INSN(clearpcr, 0x3073, 0x707f)
-DECLARE_INSN(fmadd_h, 0x4000043, 0x600007f)
 DECLARE_INSN(fmv_x_s, 0xe0000053, 0xfff0707f)
 DECLARE_INSN(fsgnjn_d, 0x32000053, 0xfe00707f)
 DECLARE_INSN(fnmadd_s, 0x4f, 0x600007f)
 DECLARE_INSN(jal, 0x67, 0x7f)
 DECLARE_INSN(lwu, 0x6003, 0x707f)
 DECLARE_INSN(fmv_x_d, 0xe2000053, 0xfff0707f)
-DECLARE_INSN(fmv_x_h, 0xe4000053, 0xfff0707f)
+DECLARE_INSN(fnmadd_d, 0x200004f, 0x600007f)
 DECLARE_INSN(amoadd_d, 0x302f, 0xf800707f)
 DECLARE_INSN(lr_d, 0x1000302f, 0xf9f0707f)
 DECLARE_INSN(fcvt_w_s, 0x50000053, 0xfff0007f)
@@ -124,11 +104,8 @@ DECLARE_INSN(mulhsu, 0x2002033, 0xfe00707f)
 DECLARE_INSN(amoadd_w, 0x202f, 0xf800707f)
 DECLARE_INSN(fcvt_d_lu, 0x6a000053, 0xfff0007f)
 DECLARE_INSN(lr_w, 0x1000202f, 0xf9f0707f)
-DECLARE_INSN(fcvt_h_l, 0x64000053, 0xfff0007f)
 DECLARE_INSN(fcvt_w_d, 0x52000053, 0xfff0007f)
-DECLARE_INSN(fsub_h, 0xc000053, 0xfe00007f)
 DECLARE_INSN(slt, 0x2033, 0xfe00707f)
-DECLARE_INSN(fnmadd_d, 0x200004f, 0x600007f)
 DECLARE_INSN(sllw, 0x103b, 0xfe00707f)
 DECLARE_INSN(amoor_d, 0x4000302f, 0xf800707f)
 DECLARE_INSN(slti, 0x2013, 0x707f)
@@ -136,21 +113,16 @@ DECLARE_INSN(remu, 0x2007033, 0xfe00707f)
 DECLARE_INSN(flw, 0x2007, 0x707f)
 DECLARE_INSN(remw, 0x200603b, 0xfe00707f)
 DECLARE_INSN(sltu, 0x3033, 0xfe00707f)
-DECLARE_INSN(flh, 0x1007, 0x707f)
 DECLARE_INSN(slli, 0x40001013, 0xfc00707f)
 DECLARE_INSN(amoor_w, 0x4000202f, 0xf800707f)
-DECLARE_INSN(fle_h, 0xbc000053, 0xfe00707f)
 DECLARE_INSN(beq, 0x63, 0x707f)
 DECLARE_INSN(fld, 0x3007, 0x707f)
 DECLARE_INSN(fsub_s, 0x8000053, 0xfe00007f)
 DECLARE_INSN(and, 0x7033, 0xfe00707f)
-DECLARE_INSN(fcvt_h_lu, 0x6c000053, 0xfff0007f)
+DECLARE_INSN(fmv_d_x, 0xf2000053, 0xfff0707f)
 DECLARE_INSN(lbu, 0x4003, 0x707f)
 DECLARE_INSN(syscall, 0x77, 0xffffffff)
 DECLARE_INSN(fsgnj_s, 0x28000053, 0xfe00707f)
-DECLARE_INSN(fle_s, 0xb8000053, 0xfe00707f)
-DECLARE_INSN(fsgnj_h, 0x2c000053, 0xfe00707f)
-DECLARE_INSN(fsgnjx_h, 0x3c000053, 0xfe00707f)
 DECLARE_INSN(amomax_w, 0xa000202f, 0xf800707f)
 DECLARE_INSN(fsgnj_d, 0x2a000053, 0xfe00707f)
 DECLARE_INSN(mulhu, 0x2003033, 0xfe00707f)
@@ -167,24 +139,19 @@ DECLARE_INSN(fsqrt_s, 0x20000053, 0xfff0007f)
 DECLARE_INSN(amomin_w, 0x8000202f, 0xf800707f)
 DECLARE_INSN(fsgnjn_s, 0x30000053, 0xfe00707f)
 DECLARE_INSN(amoswap_d, 0x800302f, 0xf800707f)
-DECLARE_INSN(fsgnjn_h, 0x34000053, 0xfe00707f)
 DECLARE_INSN(fsqrt_d, 0x22000053, 0xfff0007f)
 DECLARE_INSN(fmadd_d, 0x2000043, 0x600007f)
 DECLARE_INSN(divw, 0x200403b, 0xfe00707f)
 DECLARE_INSN(amomin_d, 0x8000302f, 0xf800707f)
 DECLARE_INSN(divu, 0x2005033, 0xfe00707f)
 DECLARE_INSN(amoswap_w, 0x800202f, 0xf800707f)
-DECLARE_INSN(fsqrt_h, 0x24000053, 0xfff0007f)
 DECLARE_INSN(jalr, 0x6f, 0x707f)
 DECLARE_INSN(fadd_s, 0x53, 0xfe00007f)
 DECLARE_INSN(fsd, 0x3027, 0x707f)
-DECLARE_INSN(fsh, 0x1027, 0x707f)
 DECLARE_INSN(sw, 0x2023, 0x707f)
 DECLARE_INSN(fmsub_s, 0x47, 0x600007f)
 DECLARE_INSN(lhu, 0x5003, 0x707f)
 DECLARE_INSN(sh, 0x1023, 0x707f)
-DECLARE_INSN(fcvt_lu_h, 0x4c000053, 0xfff0007f)
-DECLARE_INSN(fmsub_h, 0x4000047, 0x600007f)
 DECLARE_INSN(fsw, 0x2027, 0x707f)
 DECLARE_INSN(sb, 0x23, 0x707f)
 DECLARE_INSN(fmsub_d, 0x2000047, 0x600007f)

From 826fc1719aaabcf11651b4ede4d98109ad9dc05a Mon Sep 17 00:00:00 2001
From: Albert Ou <a_ou@eecs.berkeley.edu>
Date: Mon, 4 Nov 2013 22:31:01 -0800
Subject: [PATCH 3/7] Implement "half-baked" half-precision instruction subset
 for Hwacha

---
 hwacha/cvt16.cc                        | 128 +++++++++++++++++++++++++
 hwacha/cvt16.h                         |   9 ++
 hwacha/decode_hwacha_ut_half.h         |  15 +++
 hwacha/hwacha.mk.in                    |  11 ++-
 hwacha/insn_template_hwacha_ut_half.cc |  25 +++++
 hwacha/insns_ut_half/ut_fadd_h.h       |   4 +
 hwacha/insns_ut_half/ut_fcvt_d_h.h     |   4 +
 hwacha/insns_ut_half/ut_fcvt_h_d.h     |   4 +
 hwacha/insns_ut_half/ut_fcvt_h_l.h     |   5 +
 hwacha/insns_ut_half/ut_fcvt_h_lu.h    |   5 +
 hwacha/insns_ut_half/ut_fcvt_h_s.h     |   3 +
 hwacha/insns_ut_half/ut_fcvt_h_w.h     |   4 +
 hwacha/insns_ut_half/ut_fcvt_h_wu.h    |   4 +
 hwacha/insns_ut_half/ut_fcvt_l_h.h     |   5 +
 hwacha/insns_ut_half/ut_fcvt_lu_h.h    |   5 +
 hwacha/insns_ut_half/ut_fcvt_s_h.h     |   3 +
 hwacha/insns_ut_half/ut_fcvt_w_h.h     |   4 +
 hwacha/insns_ut_half/ut_fcvt_wu_h.h    |   4 +
 hwacha/insns_ut_half/ut_fdiv_h.h       |   4 +
 hwacha/insns_ut_half/ut_feq_h.h        |   3 +
 hwacha/insns_ut_half/ut_fle_h.h        |   3 +
 hwacha/insns_ut_half/ut_flh.h          |   2 +
 hwacha/insns_ut_half/ut_flt_h.h        |   3 +
 hwacha/insns_ut_half/ut_fmadd_h.h      |   4 +
 hwacha/insns_ut_half/ut_fmax_h.h       |   4 +
 hwacha/insns_ut_half/ut_fmin_h.h       |   4 +
 hwacha/insns_ut_half/ut_fmsub_h.h      |   4 +
 hwacha/insns_ut_half/ut_fmul_h.h       |   4 +
 hwacha/insns_ut_half/ut_fmv_h_x.h      |   2 +
 hwacha/insns_ut_half/ut_fmv_x_h.h      |   2 +
 hwacha/insns_ut_half/ut_fnmadd_h.h     |   4 +
 hwacha/insns_ut_half/ut_fnmsub_h.h     |   4 +
 hwacha/insns_ut_half/ut_fsgnj_h.h      |   2 +
 hwacha/insns_ut_half/ut_fsgnjn_h.h     |   2 +
 hwacha/insns_ut_half/ut_fsgnjx_h.h     |   2 +
 hwacha/insns_ut_half/ut_fsh.h          |   2 +
 hwacha/insns_ut_half/ut_fsqrt_h.h      |   4 +
 hwacha/insns_ut_half/ut_fsub_h.h       |   4 +
 hwacha/opcodes_hwacha_ut_half.h        |  33 +++++++
 39 files changed, 336 insertions(+), 2 deletions(-)
 create mode 100644 hwacha/cvt16.cc
 create mode 100644 hwacha/cvt16.h
 create mode 100644 hwacha/decode_hwacha_ut_half.h
 create mode 100644 hwacha/insn_template_hwacha_ut_half.cc
 create mode 100644 hwacha/insns_ut_half/ut_fadd_h.h
 create mode 100644 hwacha/insns_ut_half/ut_fcvt_d_h.h
 create mode 100644 hwacha/insns_ut_half/ut_fcvt_h_d.h
 create mode 100644 hwacha/insns_ut_half/ut_fcvt_h_l.h
 create mode 100644 hwacha/insns_ut_half/ut_fcvt_h_lu.h
 create mode 100644 hwacha/insns_ut_half/ut_fcvt_h_s.h
 create mode 100644 hwacha/insns_ut_half/ut_fcvt_h_w.h
 create mode 100644 hwacha/insns_ut_half/ut_fcvt_h_wu.h
 create mode 100644 hwacha/insns_ut_half/ut_fcvt_l_h.h
 create mode 100644 hwacha/insns_ut_half/ut_fcvt_lu_h.h
 create mode 100644 hwacha/insns_ut_half/ut_fcvt_s_h.h
 create mode 100644 hwacha/insns_ut_half/ut_fcvt_w_h.h
 create mode 100644 hwacha/insns_ut_half/ut_fcvt_wu_h.h
 create mode 100644 hwacha/insns_ut_half/ut_fdiv_h.h
 create mode 100644 hwacha/insns_ut_half/ut_feq_h.h
 create mode 100644 hwacha/insns_ut_half/ut_fle_h.h
 create mode 100644 hwacha/insns_ut_half/ut_flh.h
 create mode 100644 hwacha/insns_ut_half/ut_flt_h.h
 create mode 100644 hwacha/insns_ut_half/ut_fmadd_h.h
 create mode 100644 hwacha/insns_ut_half/ut_fmax_h.h
 create mode 100644 hwacha/insns_ut_half/ut_fmin_h.h
 create mode 100644 hwacha/insns_ut_half/ut_fmsub_h.h
 create mode 100644 hwacha/insns_ut_half/ut_fmul_h.h
 create mode 100644 hwacha/insns_ut_half/ut_fmv_h_x.h
 create mode 100644 hwacha/insns_ut_half/ut_fmv_x_h.h
 create mode 100644 hwacha/insns_ut_half/ut_fnmadd_h.h
 create mode 100644 hwacha/insns_ut_half/ut_fnmsub_h.h
 create mode 100644 hwacha/insns_ut_half/ut_fsgnj_h.h
 create mode 100644 hwacha/insns_ut_half/ut_fsgnjn_h.h
 create mode 100644 hwacha/insns_ut_half/ut_fsgnjx_h.h
 create mode 100644 hwacha/insns_ut_half/ut_fsh.h
 create mode 100644 hwacha/insns_ut_half/ut_fsqrt_h.h
 create mode 100644 hwacha/insns_ut_half/ut_fsub_h.h
 create mode 100644 hwacha/opcodes_hwacha_ut_half.h

diff --git a/hwacha/cvt16.cc b/hwacha/cvt16.cc
new file mode 100644
index 00000000..01768228
--- /dev/null
+++ b/hwacha/cvt16.cc
@@ -0,0 +1,128 @@
+#include "cvt16.h"
+
+#define H_BIAS    (UINT16_C(0xf))
+#define H_F_MASK  (UINT16_C(0x03FF))
+#define H_E_MASK  (UINT16_C(0x7C00))
+#define H_E_SHIFT (10)
+#define H_S_MASK  (UINT16_C(0x8000))
+
+#define H_QNAN    (H_F_MASK)
+
+#define S_BIAS    (UINT32_C(0x7F))
+#define S_F_MASK  (UINT32_C(0x007fffff))
+#define S_E_MASK  (UINT32_C(0x7f800000))
+#define S_E_SHIFT (23)
+#define S_S_MASK  (UINT32_C(0x80000000))
+
+#define S_QNAN    (S_F_MASK)
+
+#define PAD  (S_E_SHIFT - H_E_SHIFT)
+
+uint_fast32_t cvt_hs(uint_fast16_t x)
+{
+#define MSB (UINT32_C(0x00800000))
+	uint_fast32_t frac, exp, sign;
+	frac = (x & H_F_MASK) << PAD;
+	exp  = (x & H_E_MASK);
+	sign = (x & H_S_MASK);
+
+	switch (exp) {
+	case 0:
+		if (frac) { /* Denormal */
+			exp = S_BIAS - 14;
+			/* Adjust fraction for implicit leading 1-bit */
+			for (; !(frac & MSB); frac <<= 1, exp--);
+			frac &= ~(MSB);
+			exp <<= S_E_SHIFT;
+		}
+		break;
+
+	case H_E_MASK: /* Infinity and NaN */
+		exp = S_E_MASK;
+		if (frac) { /* Set padding bits for NaN */
+			frac |= (1 << PAD) - 1;
+		}
+		break;
+	default:
+		exp += (S_BIAS - H_BIAS) << H_E_SHIFT; /* Re-bias */
+		exp <<= PAD;
+	}
+	return (sign << 16) | exp | frac;
+#undef MSB
+}
+
+enum riscv_rm {
+	RNE = 0, /* Round to nearest; ties to even */
+	RTZ = 1, /* Round towards zero (truncate) */
+	RDN = 2, /* Round towards negative infinity (down) */
+	RUP = 3, /* Round towards positive infinity (up) */
+	RMM = 4, /* Round to nearest; ties to max magnitude */
+};
+
+/*
+ * LSB           : frac[13]
+ * Guard bit  (G): frac[12]
+ * Round bit  (R): frac[11]
+ * Sticky bit (S): OR of frac[10..0]
+ *
+ * RTZ:
+ *   truncate
+ * RUP:
+ *   000 : exact
+ *  else : round up
+ * RDN:
+ *   000 : exact
+ *  else : round down
+ * RNE:
+ *   0xx : round down 
+ *   100 : tie; round up if LSB is 1
+ *   101 : round up
+ *   110 : round up
+ *   111 : round up
+ */
+uint_fast16_t cvt_sh(uint_fast32_t x, int rm)
+{
+#define MSB UINT16_C(0x0400)
+	uint_fast32_t frac, exp, sign;
+	int e;
+	sign = (x & S_S_MASK) >> 16;
+	exp = (x & S_E_MASK);
+	if (exp && exp != S_E_MASK) {
+		int inc;
+		inc = 0;
+		switch (rm) {
+		case RNE:
+			/* Round up if G is set and either R, S,
+			   or the bit before G is non-zero */
+			inc = (x & 0x1000) && (x & 0x2fff);
+			break;
+		case RUP:
+			inc = ((x & 0x1fff) != 0) && (!sign);
+			break;
+		case RDN:
+			inc = ((x & 0x1fff) != 0) && sign;
+			break;
+		}
+		x += inc << PAD;
+		exp = (x & S_E_MASK);
+	}
+	frac = (x & S_F_MASK) >> PAD;
+
+	e = (exp >> S_E_SHIFT) - S_BIAS;
+	if (e < -24) { /* Round to zero */
+		return sign;
+	} else if (e < -14) { /* Denormal */
+		frac = (frac | MSB) >> (-e - 14);
+		return sign | frac;
+	} else if (e < 16) {
+		exp = (e + H_BIAS) << H_E_SHIFT;
+	} else if (e < 127) { /* Round to infinity */
+		exp = H_E_MASK;
+		frac = 0;
+	} else {
+		/* Infinity and NaN */
+	}
+	return sign | exp | frac;
+#undef MSB
+}
+
diff --git a/hwacha/cvt16.h b/hwacha/cvt16.h
new file mode 100644
index 00000000..1132f3f5
--- /dev/null
+++ b/hwacha/cvt16.h
@@ -0,0 +1,9 @@
+#ifndef _CVT16_H
+#define _CVT16_H
+
+#include <cstdint>
+
+extern uint_fast32_t cvt_hs(uint_fast16_t);
+extern uint_fast16_t cvt_sh(uint_fast32_t, int);
+
+#endif
diff --git a/hwacha/decode_hwacha_ut_half.h b/hwacha/decode_hwacha_ut_half.h
new file mode 100644
index 00000000..b4bff21e
--- /dev/null
+++ b/hwacha/decode_hwacha_ut_half.h
@@ -0,0 +1,15 @@
+#ifndef _DECODE_HWACHA_UT_HALF_H
+#define _DECODE_HWACHA_UT_HALF_H
+
+#include "decode_hwacha_ut.h"
+#include "cvt16.h"
+
+#define HFRS1 cvt_hs(FRS1)
+#define HFRS2 cvt_hs(FRS2)
+#define HFRS3 cvt_hs(FRS3)
+
+#define WRITE_HFRD(value) write_frd(h, insn, UTIDX, cvt_sh(value, RM))
+
+#define sext16(x) ((sreg_t)(int16_t)(x))
+
+#endif
diff --git a/hwacha/hwacha.mk.in b/hwacha/hwacha.mk.in
index bf16b6fb..487259dd 100644
--- a/hwacha/hwacha.mk.in
+++ b/hwacha/hwacha.mk.in
@@ -1,4 +1,4 @@
-get_insn_list = $(shell cat $(1) | sed 's/DECLARE_INSN(\(.*\),.*,.*)/\1/')
+get_insn_list = $(shell sed 's/DECLARE_INSN(\(.*\),.*,.*)/\1/' $(1))
 get_opcode = $(shell grep \\\<$(2)\\\> $(1) | sed 's/DECLARE_INSN(.*,\(.*\),.*)/\1/')
 
 hwacha_subproject_deps = \
@@ -9,17 +9,19 @@ hwacha_install_prog_srcs = \
 
 hwacha_hdrs = \
 	hwacha.h \
-	hwacha_xcpt.h \
 	decode_hwacha.h \
 	decode_hwacha_ut.h \
+	decode_hwacha_ut_half.h \
 	opcodes_hwacha.h \
 	opcodes_hwacha_ut.h \
+	opcodes_hwacha_ut_half.h \
 
 hwacha_srcs = \
 	hwacha.cc \
 	hwacha_disasm.cc \
 	$(hwacha_gen_srcs) \
 	$(hwacha_ut_gen_srcs) \
+	$(hwacha_ut_half_gen_srcs) \
 
 hwacha_test_srcs =
 
@@ -35,3 +37,8 @@ hwacha_ut_gen_srcs = \
 $(hwacha_ut_gen_srcs): %.cc: insns_ut/%.h insn_template_hwacha_ut.cc
 	sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/hwacha/insn_template_hwacha_ut.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/hwacha/opcodes_hwacha_ut.h,$(subst .cc,,$@))/' > $@
 
+hwacha_ut_half_gen_srcs = \
+	$(addsuffix .cc, $(call get_insn_list,$(src_dir)/hwacha/opcodes_hwacha_ut_half.h))
+
+$(hwacha_ut_half_gen_srcs): %.cc: insns_ut_half/%.h insn_template_hwacha_ut_half.cc
+	sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/hwacha/insn_template_hwacha_ut_half.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/hwacha/opcodes_hwacha_ut_half.h,$(subst .cc,,$@))/' > $@
diff --git a/hwacha/insn_template_hwacha_ut_half.cc b/hwacha/insn_template_hwacha_ut_half.cc
new file mode 100644
index 00000000..12a0fb20
--- /dev/null
+++ b/hwacha/insn_template_hwacha_ut_half.cc
@@ -0,0 +1,25 @@
+// See LICENSE for license details.
+
+#include "config.h"
+#include "processor.h"
+#include "mmu.h"
+#include "softfloat.h"
+#include "platform.h" // softfloat isNaNF32UI, etc.
+#include "internals.h" // ditto
+#include "hwacha.h"
+#include "decode_hwacha_ut_half.h"
+#include "cvt16.h"
+#include <assert.h>
+
+reg_t hwacha_NAME(processor_t* p, insn_t insn, reg_t pc)
+{
+  int xprlen = 64;
+  reg_t npc = sext_xprlen(pc + insn_length(OPCODE));
+  hwacha_t* h = static_cast<hwacha_t*>(p->get_extension());
+  do {
+    #include "insns_ut_half/NAME.h"
+    WRITE_UTIDX(UTIDX+1);
+  } while (UTIDX < VL);
+  WRITE_UTIDX(0);
+  return npc;
+}
diff --git a/hwacha/insns_ut_half/ut_fadd_h.h b/hwacha/insns_ut_half/ut_fadd_h.h
new file mode 100644
index 00000000..8192562e
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fadd_h.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_HFRD(f32_mulAdd(HFRS1, 0x3f800000, HFRS2));
+set_fp_exceptions;
diff --git a/hwacha/insns_ut_half/ut_fcvt_d_h.h b/hwacha/insns_ut_half/ut_fcvt_d_h.h
new file mode 100644
index 00000000..9251ae90
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fcvt_d_h.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_FRD(f32_to_f64(HFRS1));
+set_fp_exceptions;
diff --git a/hwacha/insns_ut_half/ut_fcvt_h_d.h b/hwacha/insns_ut_half/ut_fcvt_h_d.h
new file mode 100644
index 00000000..89dc473c
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fcvt_h_d.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_HFRD(f64_to_f32(FRS1));
+set_fp_exceptions;
diff --git a/hwacha/insns_ut_half/ut_fcvt_h_l.h b/hwacha/insns_ut_half/ut_fcvt_h_l.h
new file mode 100644
index 00000000..fe75c274
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fcvt_h_l.h
@@ -0,0 +1,5 @@
+require_xpr64;
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_HFRD(i64_to_f32(RS1));
+set_fp_exceptions;
diff --git a/hwacha/insns_ut_half/ut_fcvt_h_lu.h b/hwacha/insns_ut_half/ut_fcvt_h_lu.h
new file mode 100644
index 00000000..38fc8a7e
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fcvt_h_lu.h
@@ -0,0 +1,5 @@
+require_xpr64;
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_HFRD(ui64_to_f32(RS1));
+set_fp_exceptions;
diff --git a/hwacha/insns_ut_half/ut_fcvt_h_s.h b/hwacha/insns_ut_half/ut_fcvt_h_s.h
new file mode 100644
index 00000000..ee49e1b8
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fcvt_h_s.h
@@ -0,0 +1,3 @@
+require_fp;
+WRITE_FRD(cvt_sh(FRS1, RM));
+set_fp_exceptions;
diff --git a/hwacha/insns_ut_half/ut_fcvt_h_w.h b/hwacha/insns_ut_half/ut_fcvt_h_w.h
new file mode 100644
index 00000000..383a3c09
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fcvt_h_w.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_HFRD(i32_to_f32((int32_t)RS1));
+set_fp_exceptions;
diff --git a/hwacha/insns_ut_half/ut_fcvt_h_wu.h b/hwacha/insns_ut_half/ut_fcvt_h_wu.h
new file mode 100644
index 00000000..228b25ae
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fcvt_h_wu.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_HFRD(ui32_to_f32((uint32_t)RS1));
+set_fp_exceptions;
diff --git a/hwacha/insns_ut_half/ut_fcvt_l_h.h b/hwacha/insns_ut_half/ut_fcvt_l_h.h
new file mode 100644
index 00000000..1551ce2e
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fcvt_l_h.h
@@ -0,0 +1,5 @@
+require_xpr64;
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_RD(f32_to_i64(HFRS1, RM, true));
+set_fp_exceptions;
diff --git a/hwacha/insns_ut_half/ut_fcvt_lu_h.h b/hwacha/insns_ut_half/ut_fcvt_lu_h.h
new file mode 100644
index 00000000..b2fc5fdc
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fcvt_lu_h.h
@@ -0,0 +1,5 @@
+require_xpr64;
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_RD(f32_to_ui64(HFRS1, RM, true));
+set_fp_exceptions;
diff --git a/hwacha/insns_ut_half/ut_fcvt_s_h.h b/hwacha/insns_ut_half/ut_fcvt_s_h.h
new file mode 100644
index 00000000..f779da8a
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fcvt_s_h.h
@@ -0,0 +1,3 @@
+require_fp;
+WRITE_FRD(HFRS1);
+set_fp_exceptions;
diff --git a/hwacha/insns_ut_half/ut_fcvt_w_h.h b/hwacha/insns_ut_half/ut_fcvt_w_h.h
new file mode 100644
index 00000000..5a2f0841
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fcvt_w_h.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_RD(sext32(f32_to_i32(HFRS1, RM, true)));
+set_fp_exceptions;
diff --git a/hwacha/insns_ut_half/ut_fcvt_wu_h.h b/hwacha/insns_ut_half/ut_fcvt_wu_h.h
new file mode 100644
index 00000000..537f50aa
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fcvt_wu_h.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_RD(sext32(f32_to_ui32(HFRS1, RM, true)));
+set_fp_exceptions;
diff --git a/hwacha/insns_ut_half/ut_fdiv_h.h b/hwacha/insns_ut_half/ut_fdiv_h.h
new file mode 100644
index 00000000..924b0c7b
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fdiv_h.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_HFRD(f32_div(HFRS1, HFRS2));
+set_fp_exceptions;
diff --git a/hwacha/insns_ut_half/ut_feq_h.h b/hwacha/insns_ut_half/ut_feq_h.h
new file mode 100644
index 00000000..a6b47073
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_feq_h.h
@@ -0,0 +1,3 @@
+require_fp;
+WRITE_RD(f32_eq(HFRS1, HFRS2));
+set_fp_exceptions;
diff --git a/hwacha/insns_ut_half/ut_fle_h.h b/hwacha/insns_ut_half/ut_fle_h.h
new file mode 100644
index 00000000..2c17204d
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fle_h.h
@@ -0,0 +1,3 @@
+require_fp;
+WRITE_RD(f32_le(HFRS1, HFRS2));
+set_fp_exceptions;
diff --git a/hwacha/insns_ut_half/ut_flh.h b/hwacha/insns_ut_half/ut_flh.h
new file mode 100644
index 00000000..90872edc
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_flh.h
@@ -0,0 +1,2 @@
+require_fp;
+WRITE_FRD(MMU.load_int16(RS1 + insn.i_imm()));
diff --git a/hwacha/insns_ut_half/ut_flt_h.h b/hwacha/insns_ut_half/ut_flt_h.h
new file mode 100644
index 00000000..39a0393f
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_flt_h.h
@@ -0,0 +1,3 @@
+require_fp;
+WRITE_RD(f32_lt(HFRS1, HFRS2));
+set_fp_exceptions;
diff --git a/hwacha/insns_ut_half/ut_fmadd_h.h b/hwacha/insns_ut_half/ut_fmadd_h.h
new file mode 100644
index 00000000..cfbd82e2
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fmadd_h.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_HFRD(f32_mulAdd(HFRS1, HFRS2, HFRS3));
+set_fp_exceptions;
diff --git a/hwacha/insns_ut_half/ut_fmax_h.h b/hwacha/insns_ut_half/ut_fmax_h.h
new file mode 100644
index 00000000..32d3aa68
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fmax_h.h
@@ -0,0 +1,4 @@
+require_fp;
+WRITE_HFRD(isNaNF32UI(HFRS2) || f32_le_quiet(HFRS2,HFRS1) /* && FRS1 not NaN */
+      ? HFRS1 : HFRS2);
+set_fp_exceptions;
diff --git a/hwacha/insns_ut_half/ut_fmin_h.h b/hwacha/insns_ut_half/ut_fmin_h.h
new file mode 100644
index 00000000..a6a7cc3e
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fmin_h.h
@@ -0,0 +1,4 @@
+require_fp;
+WRITE_HFRD(isNaNF32UI(HFRS2) || f32_lt_quiet(HFRS1,HFRS2) /* && FRS1 not NaN */
+      ? HFRS1 : HFRS2);
+set_fp_exceptions;
diff --git a/hwacha/insns_ut_half/ut_fmsub_h.h b/hwacha/insns_ut_half/ut_fmsub_h.h
new file mode 100644
index 00000000..323a8d04
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fmsub_h.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_HFRD(f32_mulAdd(HFRS1, HFRS2, HFRS3 ^ (uint32_t)INT32_MIN));
+set_fp_exceptions;
diff --git a/hwacha/insns_ut_half/ut_fmul_h.h b/hwacha/insns_ut_half/ut_fmul_h.h
new file mode 100644
index 00000000..669dd0ee
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fmul_h.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_HFRD(f32_mulAdd(HFRS1, HFRS2, (HFRS1 ^ HFRS2) & (uint32_t)INT32_MIN));
+set_fp_exceptions;
diff --git a/hwacha/insns_ut_half/ut_fmv_h_x.h b/hwacha/insns_ut_half/ut_fmv_h_x.h
new file mode 100644
index 00000000..f3eac828
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fmv_h_x.h
@@ -0,0 +1,2 @@
+require_fp;
+WRITE_FRD(RS1);
diff --git a/hwacha/insns_ut_half/ut_fmv_x_h.h b/hwacha/insns_ut_half/ut_fmv_x_h.h
new file mode 100644
index 00000000..d0a84bc9
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fmv_x_h.h
@@ -0,0 +1,2 @@
+require_fp;
+WRITE_RD(sext16(FRS1));
diff --git a/hwacha/insns_ut_half/ut_fnmadd_h.h b/hwacha/insns_ut_half/ut_fnmadd_h.h
new file mode 100644
index 00000000..f17cd8e8
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fnmadd_h.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_HFRD(f32_mulAdd(HFRS1 ^ (uint32_t)INT32_MIN, HFRS2, HFRS3 ^ (uint32_t)INT32_MIN));
+set_fp_exceptions;
diff --git a/hwacha/insns_ut_half/ut_fnmsub_h.h b/hwacha/insns_ut_half/ut_fnmsub_h.h
new file mode 100644
index 00000000..9a3161a0
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fnmsub_h.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_HFRD(f32_mulAdd(HFRS1 ^ (uint32_t)INT32_MIN, HFRS2, HFRS3));
+set_fp_exceptions;
diff --git a/hwacha/insns_ut_half/ut_fsgnj_h.h b/hwacha/insns_ut_half/ut_fsgnj_h.h
new file mode 100644
index 00000000..152d02b7
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fsgnj_h.h
@@ -0,0 +1,2 @@
+require_fp;
+WRITE_FRD((FRS1 &~ (uint16_t)INT16_MIN) | (FRS2 & (uint16_t)INT16_MIN));
diff --git a/hwacha/insns_ut_half/ut_fsgnjn_h.h b/hwacha/insns_ut_half/ut_fsgnjn_h.h
new file mode 100644
index 00000000..b098150c
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fsgnjn_h.h
@@ -0,0 +1,2 @@
+require_fp;
+WRITE_FRD((FRS1 &~ (uint32_t)INT32_MIN) | ((~FRS2) & (uint32_t)INT32_MIN));
diff --git a/hwacha/insns_ut_half/ut_fsgnjx_h.h b/hwacha/insns_ut_half/ut_fsgnjx_h.h
new file mode 100644
index 00000000..2b6d7ac8
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fsgnjx_h.h
@@ -0,0 +1,2 @@
+require_fp;
+WRITE_FRD(FRS1 ^ (FRS2 & (uint16_t)INT16_MIN));
diff --git a/hwacha/insns_ut_half/ut_fsh.h b/hwacha/insns_ut_half/ut_fsh.h
new file mode 100644
index 00000000..945d3e39
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fsh.h
@@ -0,0 +1,2 @@
+require_fp;
+MMU.store_uint16(RS1 + insn.s_imm(), FRS2);
diff --git a/hwacha/insns_ut_half/ut_fsqrt_h.h b/hwacha/insns_ut_half/ut_fsqrt_h.h
new file mode 100644
index 00000000..f8b83fb7
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fsqrt_h.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_HFRD(f32_sqrt(HFRS1));
+set_fp_exceptions;
diff --git a/hwacha/insns_ut_half/ut_fsub_h.h b/hwacha/insns_ut_half/ut_fsub_h.h
new file mode 100644
index 00000000..39cebbef
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_fsub_h.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+WRITE_HFRD(f32_mulAdd(HFRS1, 0x3f800000, HFRS2 ^ (uint32_t)INT32_MIN));
+set_fp_exceptions;
diff --git a/hwacha/opcodes_hwacha_ut_half.h b/hwacha/opcodes_hwacha_ut_half.h
new file mode 100644
index 00000000..b869a072
--- /dev/null
+++ b/hwacha/opcodes_hwacha_ut_half.h
@@ -0,0 +1,33 @@
+DECLARE_INSN(ut_fcvt_h_lu, 0x6c000053, 0xfff0007f)
+DECLARE_INSN(ut_fmin_h, 0xc4000053, 0xfe00707f)
+DECLARE_INSN(ut_fcvt_wu_h, 0x5c000053, 0xfff0007f)
+DECLARE_INSN(ut_fdiv_h, 0x1c000053, 0xfe00007f)
+DECLARE_INSN(ut_fcvt_h_wu, 0x7c000053, 0xfff0007f)
+DECLARE_INSN(ut_fsgnj_h, 0x2c000053, 0xfe00707f)
+DECLARE_INSN(ut_fnmsub_h, 0x400004b, 0x600007f)
+DECLARE_INSN(ut_fle_h, 0xbc000053, 0xfe00707f)
+DECLARE_INSN(ut_fcvt_l_h, 0x44000053, 0xfff0007f)
+DECLARE_INSN(ut_fnmadd_h, 0x400004f, 0x600007f)
+DECLARE_INSN(ut_fcvt_h_s, 0x90000053, 0xfff0007f)
+DECLARE_INSN(ut_fcvt_h_w, 0x74000053, 0xfff0007f)
+DECLARE_INSN(ut_fcvt_d_h, 0x8c000053, 0xfff0007f)
+DECLARE_INSN(ut_fmax_h, 0xcc000053, 0xfe00707f)
+DECLARE_INSN(ut_fcvt_lu_h, 0x4c000053, 0xfff0007f)
+DECLARE_INSN(ut_fcvt_h_l, 0x64000053, 0xfff0007f)
+DECLARE_INSN(ut_fmv_x_h, 0xe4000053, 0xfff0707f)
+DECLARE_INSN(ut_fcvt_h_d, 0x92000053, 0xfff0007f)
+DECLARE_INSN(ut_flt_h, 0xb4000053, 0xfe00707f)
+DECLARE_INSN(ut_fadd_h, 0x4000053, 0xfe00007f)
+DECLARE_INSN(ut_fcvt_s_h, 0x84000053, 0xfff0007f)
+DECLARE_INSN(ut_fcvt_w_h, 0x54000053, 0xfff0007f)
+DECLARE_INSN(ut_fmul_h, 0x14000053, 0xfe00007f)
+DECLARE_INSN(ut_fmadd_h, 0x4000043, 0x600007f)
+DECLARE_INSN(ut_fsqrt_h, 0x24000053, 0xfff0007f)
+DECLARE_INSN(ut_fsgnjn_h, 0x34000053, 0xfe00707f)
+DECLARE_INSN(ut_fsub_h, 0xc000053, 0xfe00007f)
+DECLARE_INSN(ut_fsh, 0x1027, 0x707f)
+DECLARE_INSN(ut_fsgnjx_h, 0x3c000053, 0xfe00707f)
+DECLARE_INSN(ut_flh, 0x1007, 0x707f)
+DECLARE_INSN(ut_fmsub_h, 0x4000047, 0x600007f)
+DECLARE_INSN(ut_feq_h, 0xac000053, 0xfe00707f)
+DECLARE_INSN(ut_fmv_h_x, 0xf4000053, 0xfff0707f)

From c258e24c0a35632d76b7bebc10ab9c382ccd4823 Mon Sep 17 00:00:00 2001
From: Albert Ou <a_ou@eecs.berkeley.edu>
Date: Mon, 4 Nov 2013 22:33:20 -0800
Subject: [PATCH 4/7] Re-add Hwacha header file

---
 hwacha/hwacha.mk.in | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hwacha/hwacha.mk.in b/hwacha/hwacha.mk.in
index 487259dd..bcda2abc 100644
--- a/hwacha/hwacha.mk.in
+++ b/hwacha/hwacha.mk.in
@@ -9,6 +9,7 @@ hwacha_install_prog_srcs = \
 
 hwacha_hdrs = \
 	hwacha.h \
+	hwacha_xcpt.h \
 	decode_hwacha.h \
 	decode_hwacha_ut.h \
 	decode_hwacha_ut_half.h \

From ad4269640525ffefba5ecaf4ccd41bc6b543877b Mon Sep 17 00:00:00 2001
From: Albert Ou <a_ou@eecs.berkeley.edu>
Date: Mon, 4 Nov 2013 23:25:00 -0800
Subject: [PATCH 5/7] Fix declaration of half-precision instructions

---
 hwacha/hwacha.mk.in | 1 +
 hwacha/insns/vf.h   | 1 +
 2 files changed, 2 insertions(+)

diff --git a/hwacha/hwacha.mk.in b/hwacha/hwacha.mk.in
index bcda2abc..6a15e3a1 100644
--- a/hwacha/hwacha.mk.in
+++ b/hwacha/hwacha.mk.in
@@ -20,6 +20,7 @@ hwacha_hdrs = \
 hwacha_srcs = \
 	hwacha.cc \
 	hwacha_disasm.cc \
+	cvt16.cc \
 	$(hwacha_gen_srcs) \
 	$(hwacha_ut_gen_srcs) \
 	$(hwacha_ut_half_gen_srcs) \
diff --git a/hwacha/insns/vf.h b/hwacha/insns/vf.h
index fafb8b91..7999428d 100644
--- a/hwacha/insns/vf.h
+++ b/hwacha/insns/vf.h
@@ -21,6 +21,7 @@ vf_loop:
       matched = true; \
     }
   #include "opcodes_hwacha_ut.h"
+  #include "opcodes_hwacha_ut_half.h"
   #undef DECLARE_INSN
 
   if (!matched)

From 05f9118e82283a6225534098487fa2011d065fd1 Mon Sep 17 00:00:00 2001
From: Quan Nguyen <quannguyen@berkeley.edu>
Date: Fri, 29 Nov 2013 20:10:46 -0800
Subject: [PATCH 6/7] Add vsetprec instruction prototype

---
 hwacha/decode_hwacha.h  |  1 +
 hwacha/hwacha.cc        |  1 +
 hwacha/hwacha.h         |  1 +
 hwacha/insns/vsetprec.h | 13 +++++++++++++
 hwacha/opcodes_hwacha.h |  1 +
 5 files changed, 17 insertions(+)
 create mode 100644 hwacha/insns/vsetprec.h

diff --git a/hwacha/decode_hwacha.h b/hwacha/decode_hwacha.h
index b7069fad..badf7501 100644
--- a/hwacha/decode_hwacha.h
+++ b/hwacha/decode_hwacha.h
@@ -20,6 +20,7 @@
 #define WRITE_VL(vlnext) (h->get_ct_state()->vl = (vlnext))
 #define WRITE_UTIDX(value) (h->get_ct_state()->count = (value))
 #define WRITE_VF_PC(pcnext) (h->get_ct_state()->vf_pc = (pcnext))
+#define WRITE_PREC(precision) (h->get_ct_state()->prec = (precision))
 
 #define INSN_RS1 (insn.rs1())
 #define INSN_RS2 (insn.rs2())
diff --git a/hwacha/hwacha.cc b/hwacha/hwacha.cc
index 8caf91ea..1a89d733 100644
--- a/hwacha/hwacha.cc
+++ b/hwacha/hwacha.cc
@@ -11,6 +11,7 @@ void ct_state_t::reset()
   maxvl = 32;
   vl = 0;
   count = 0;
+  prec = 64;
 
   vf_pc = -1;
 }
diff --git a/hwacha/hwacha.h b/hwacha/hwacha.h
index df0add3b..bbdd7c73 100644
--- a/hwacha/hwacha.h
+++ b/hwacha/hwacha.h
@@ -12,6 +12,7 @@ struct ct_state_t
   uint32_t maxvl;
   uint32_t vl;
   uint32_t count;
+  uint32_t prec;
 
   reg_t vf_pc;
 };
diff --git a/hwacha/insns/vsetprec.h b/hwacha/insns/vsetprec.h
new file mode 100644
index 00000000..b36f27c2
--- /dev/null
+++ b/hwacha/insns/vsetprec.h
@@ -0,0 +1,13 @@
+uint32_t prec = u.r.funct;
+switch (prec) {
+  case 16:
+  case 32:
+  case 64:
+    printf("Precision set to %d bits\n", prec);
+    WRITE_PREC(prec);
+    break;
+
+  default:
+    h->take_exception(HWACHA_CAUSE_ILLEGAL_CFG, 2);
+    break;
+}
diff --git a/hwacha/opcodes_hwacha.h b/hwacha/opcodes_hwacha.h
index e384b375..297b3afc 100644
--- a/hwacha/opcodes_hwacha.h
+++ b/hwacha/opcodes_hwacha.h
@@ -26,6 +26,7 @@ DECLARE_INSN(vlsegwu, 0xc00205b, 0x1ff0707f)
 DECLARE_INSN(vmsv, 0x200202b, 0xfff0707f)
 DECLARE_INSN(vmvv, 0x200002b, 0xfff0707f)
 DECLARE_INSN(vsetcfg, 0x200b, 0x7fff)
+DECLARE_INSN(vsetprec, 0x805b, 0xfffff)
 DECLARE_INSN(vsetvl, 0x600b, 0xfff0707f)
 DECLARE_INSN(vssegb, 0x207b, 0x1ff0707f)
 DECLARE_INSN(vssegd, 0x600207b, 0x1ff0707f)

From 64785705a4de6b49ee5e97169ff151e1d6d4598b Mon Sep 17 00:00:00 2001
From: Quan Nguyen <quannguyen@berkeley.edu>
Date: Fri, 29 Nov 2013 20:21:36 -0800
Subject: [PATCH 7/7] Remove debug printf in vsetprec

---
 hwacha/insns/vsetprec.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/hwacha/insns/vsetprec.h b/hwacha/insns/vsetprec.h
index b36f27c2..1588de6b 100644
--- a/hwacha/insns/vsetprec.h
+++ b/hwacha/insns/vsetprec.h
@@ -3,7 +3,6 @@ switch (prec) {
   case 16:
   case 32:
   case 64:
-    printf("Precision set to %d bits\n", prec);
     WRITE_PREC(prec);
     break;