From bb786db8b87915ec9a9f5d1278753032a6363be1 Mon Sep 17 00:00:00 2001
From: "Dave.Wen" <dave.wen@sifive.com>
Date: Tue, 11 Feb 2020 23:28:19 -0800
Subject: [PATCH] rvv: fix Vxrm not reflected in fcsr

---
 riscv/processor.cc | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/riscv/processor.cc b/riscv/processor.cc
index f92bb2bb..961514b1 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -846,10 +846,15 @@ reg_t processor_t::get_csr(int which)
         break;
       return state.frm;
     case CSR_FCSR:
-      require_fp;
+      {require_fp;
       if (!supports_extension('F'))
         break;
-      return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT);
+      uint32_t shared_flags = 0;
+      if (supports_extension('V'))
+            shared_flags = (VU.vxrm << FSR_VXRM_SHIFT) | (VU.vxsat << FSR_VXSAT_SHIFT);
+      return (state.fflags << FSR_AEXC_SHIFT) | (state.frm << FSR_RD_SHIFT) |
+          shared_flags;
+      }
     case CSR_INSTRET:
     case CSR_CYCLE:
       if (ctr_ok)