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@ -10,8 +10,8 @@ class processor_t; |
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// virtual memory configuration
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typedef reg_t pte_t; |
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const reg_t LEVELS = 4; |
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const reg_t PGSHIFT = 12; |
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const reg_t LEVELS = sizeof(pte_t) == sizeof(uint64_t) ? 3 : 2; |
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const reg_t PGSHIFT = 13; |
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const reg_t PGSIZE = 1 << PGSHIFT; |
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const reg_t PTIDXBITS = PGSHIFT - (sizeof(pte_t) == 8 ? 3 : 2); |
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const reg_t PPN_BITS = 8*sizeof(reg_t) - PGSHIFT; |
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@ -28,8 +28,7 @@ const reg_t PPN_BITS = 8*sizeof(reg_t) - PGSHIFT; |
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#define PTE_SW 0x100 // Supervisor Read permission
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#define PTE_SR 0x200 // Supervisor Write permission
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#define PTE_PERM (PTE_SR | PTE_SW | PTE_SX | PTE_UR | PTE_UW | PTE_UX) |
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#define PTE_PERM_SHIFT 4 |
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#define PTE_PPN_SHIFT 12 // LSB of physical page number in the PTE
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#define PTE_PPN_SHIFT 13 // LSB of physical page number in the PTE
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// this class implements a processor's port into the virtual memory system.
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// an MMU and instruction cache are maintained for simulator performance.
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